A semiconductor device is provided. The semiconductor device includes a logic region and a capacitor region, wherein the capacitor region comprises a bottom electrode disposed on a substrate; a top electrode disposed on the bottom electrode; a first inter-metal dielectric film disposed between the substrate and the bottom electrode; a second inter-metal dielectric film and a third inter-metal dielectric film disposed between the top electrode and the bottom electrode; a passivation film disposed on the top electrode, wherein the top electrode is configured to have a rounded top corner, and the bottom electrode is configured to have a sharp top corner.

An apparatus and associated method for an energy-storage device (e.g., a capacitor) having a plurality of electrically conducting electrodes including a first electrode and a second electrode separated by a non-electrically conducting region, and wherein the non-electrically conducting region further includes a non-uniform permittivity (K) value. In some embodiments, the method includes providing a substrate; fabricating a first electrode on the substrate; and fabricating a second electrode such that the second electrode is separated from the first electrode by a non-electrically conducting region, wherein the non-electrically conducting region has a non-uniform permittivity (K) value. The capacitor devices will find benefit for use in electric vehicles, of all kinds, uninterruptible power supplies, wind turbines, mobile phones, and the like requiring wide temperature ranges from several hundreds of degrees C. down to absolute zero, consumer electronics operating in a temperature range of −55 degrees C. to 125 degrees C.

Provided are an adapter board and a method for forming the same, a packaging method, and a package structure. One form of a method for forming an adapter board includes: providing a base, including an interconnect region and a capacitor region, the base including a front surface and a rear surface that are opposite each other; etching the front surface of the base, to form a first trench in the base of the interconnect region and form a second trench in the base of the capacitor region; forming a capacitor in the second trench; etching a partial thickness of the base under the first trench, to form a conductive via; forming a via interconnect structure in the conductive via; and thinning the rear surface of the base, to expose the via interconnect structure. In the embodiments and implementations of the present disclosure, the capacitor is further formed in the adapter board, so that a process of forming the capacitor and a process of forming the adapter board are integrated, and an additional step of forming the capacitor is omitted, which is beneficial to reduce processes and improve the process integration, and is further beneficial to reduce process costs and shorten the production cycle. Moreover, the functional diversity of the adapter board is further improved, so that an application scenario of the adapter board is diversified.

A display device, includes: a substrate; a thin film transistor layer including a plurality of thin film transistors; a light-emitting element layer including a plurality of light-emitting elements; a display region displaying an image; and an electronic componen being disposed on a back face side of the display region with respect to the substrate, wherein the display region includes a first display region and a second display region, each of the plurality of light-emitting elements includes a first light-emitting element and a second light-emitting element, each of the first light-emitting element and the second light-emitting element, the first electrode of the first light-emitting element includes a first reflective conductive layer, and a first upper transparent conductive layer, the first electrode of the second light-emitting element includes a second transparent conductive layer, and the second transparent conductive layer is crystallized and is thicker than the first upper transparent conductive layer.

Bonded structures having conductive features and isolation features are disclosed. In one example, a bonded structure can include a first element including a first insulating layer and at least two first conductive features disposed in the first insulating layer. The bonded structure can also include a second element including a second insulating layer and at least two second conductive features disposed in the second insulating substrate. The first element can be directly bonded to the second element with the at least two first conductive features aligned with the at least two second conductive features. The bonded structure can also include an isolation feature in the second insulating layer and between the at least two second conductive features. The isolation feature can have a dielectric constant lower than a dielectric constant of the second insulating layer.

A capacitor structure for an integrated circuit (IC) and a related method of forming are disclosed. The capacitor structure includes three electrodes. A planar bottom electrode has a first insulator layer thereover. A middle electrode includes a conductive layer over the first insulator layer and a plurality of spaced conductive pillars contacting the conductive layer. A second insulator layer extends over and between the plurality of spaced conductive pillars and contacts the conductive layer. An upper electrode extends over the second insulator layer, and hence, over and between the plurality of spaced conductive pillars. A length of the upper electrode can be controlled, in part, by the number and dimensions of the conductive pillars to increase capacitance capabilities per area.

A method of manufacturing a semiconductor structure includes: forming a first oxide layer over a landing pad layer; forming a middle patterned dielectric layer over the first oxide layer; sequentially forming a second oxide layer and a top dielectric layer over the middle patterned dielectric layer; forming a trench through the top dielectric layer, the second oxide layer and the first oxide layer; conformally forming a bottom conductive layer in the trench; removing a portion of the top dielectric layer adjacent to the trench to expose a portion of the second oxide layer beneath the portion of the top dielectric layer; and performing an etching process to remove the second oxide layer and the first oxide layer from the portion of the second oxide layer. A semiconductor structure is also provided.

Present invention relates to a method of fabricating a semiconductor device that can facilitate the processes of etching a supporter and removing a mold layer. According to the present invention, a method of fabricating a semiconductor device semiconductor device comprises: sequentially forming a substructure over a substrate and a etch stop layer over the substructure; forming a stack structure of alternately stacked mold layers and supporter layers over the etch stop layer; forming a plurality of supporter holes in the stack structure exposing the etch stop layer; forming a sacrificial layer filling each of the plurality of the supporter holes; forming a plurality of lower electrode openings exposing the substructure by etching the sacrificial layer and the stack structure; and forming a lower electrode inside the plurality of lower electrode openings.

A capacitor array includes a substrate, first pedestal container stacked capacitors, second pedestal container stacked capacitors, and third pedestal container stacked capacitors. The first pedestal container stacked capacitors extend upwardly from above the substrate and are arranged in a first row. The second pedestal container stacked capacitors extend upwardly from above the substrate and are arranged in a second row next to the first row. The third pedestal container stacked capacitors extend upwardly from above the substrate and are arranged in a third row next to the second row. A first distance between the first and second rows is less than a second distance between the second and third rows.

First and second wells are formed in a semiconductor substrate. First and second trenches in the first second wells, respectively, each extend vertically and include a central conductor insulated by a first insulating layer. A second insulating layer is formed on a top surface of the semiconductor substrate. The second insulating layer is selectively thinned over the second trench. A polysilicon layer is deposited on the second insulating layer and then lithographically patterned to form: a first polysilicon portion over the first well that is electrically connected to the central conductor of the first trench to form a first capacitor plate, a second capacitor plate formed by the first well; and a second polysilicon portion over the second well forming a floating gate electrode of a floating gate transistor of a memory cell having an access transistor whose control gate is formed by the central conductor of the second trench.