A power inverter includes a bridge circuit including a first half-bridge and a second half-bridge, each half-bridge including a high-side device and a low-side device, and a gate driver circuit connected with each gate of the high-side device and low-side power device of the first and second half-bridges and operable to provide each gate with a respective voltage to control operation of the respective power device. The gate driver is operable to provide a first voltage which is higher than a first threshold voltage of the respective power device, and a second voltage which is higher than a surge threshold of the respective power device. The surge threshold is higher than the first threshold and defines the onset of a surge current operation area of the respective power device at which the power device becomes conducts a surge current that is larger than the rated current of the device.

In a semiconductor device, a semiconductor element having a plurality of gate electrodes including a first gate electrode and a second gate electrode. An electrical connection member is electrically connected to a front surface electrode of the semiconductor element. A cell region of the semiconductor element includes a first cell region that allows a current to flow between the front surface electrode and a back surface electrode when the first gate electrode is applied with a voltage, and a second cell region that allows a current to flow between the front surface electrode and the back surface electrode when the second gate electrode is applied with a voltage. The semiconductor element and a control circuit are configured to generate a time difference in cutting off the current between the first cell region and the second cell region.

A semiconductor device has a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a first conductive layer disposed on a main surface of the first semiconductor region, and a second conductive layer disposed on a main surface of the second semiconductor region. The first conductive layer has a first diffusion layer of the first conductivity type, a plurality of second diffusion layers of the first conductivity type, the second diffusion layers having higher impurity concentration than the first diffusion layer, and a plurality of third diffusion layers of the first conductivity type that are included in the first semiconductor region, or are arranged apart from one another to contact the first and second semiconductor regions, the third diffusion layers being arranged apart from the plurality of second diffusion layers and having higher impurity concentration than the first diffusion layer.

A power device includes an active area having at least two switchable regions with different threshold voltages.

A high voltage device includes: a semiconductor layer, a well, a body region, a gate, a source, a drain, a drift oxide region, and a top region. The well is formed in the semicoducotor layer. The body region is formed in the well. The gate is formed on the well. The source and the drain are located below, outside, and at different sides of the gate, in the body region and the well respectively. The drift oxide region is formed on a drift region, wherein a bottom surface of the drift oxide region is higher than a first trench bottom surface of the first trench. The top region is formed in the well right below the drift oxide region, and is in contact with the drift oxide region.

This invention discloses a metal oxide semiconductor field effect transistor (MOSFET) device. The MOSFET device has a semiconductor substrate that supports an epitaxial layer thereon. The epitaxial layer comprises at least three layers of different dopant concentrations and wherein a middle epitaxial layer having a varying dopant concentration profile along an upward vertical direction.

The present disclosure relates to semiconductor structures and, more particularly, to extended drain MOSFET structures with a dual oxide thickness and methods of manufacture. The structure includes an extended drain metal oxide semiconductor transistor (EDMOS) comprising a gate structure with a dual oxide scheme.

A method of forming a semiconductor device includes forming a gate dielectric layer on a substrate; forming a barrier layer over the gate dielectric layer; treating the barrier layer to roughen an outer surface of the barrier layer, resulting in a treated barrier layer; and forming a metal layer over the treated barrier layer.

Power devices using refilled trenches with permanent charge at or near their sidewalls. These trenches extend vertically into a drift region.

According to an embodiment of a semiconductor device, the device includes gate trenches formed in a SiC substrate and extending lengthwise in parallel in a first direction. Rows of source regions of a first conductivity type are formed in the SiC substrate and extend lengthwise in parallel in a second direction which is transverse to the first direction. Rows of body regions of a second conductivity type opposite the first conductivity type are formed in the SiC substrate below the rows of source regions. Rows of body contact regions of the second conductivity type are formed in the SiC substrate. The rows of body contact regions extend lengthwise in parallel in the second direction. First shielding regions of the second conductivity type are formed deeper in the SiC substrate than the rows of body regions.