Provided is a semiconductor device including a semiconductor substrate having a drift region; a transistor portion having a collector region; a diode portion having a cathode region; and a boundary portion arranged between the transistor portion and the diode portion at an upper surface of the semiconductor substrate, and having the collector region, wherein the mesa portion of each of the transistor portion and the boundary portion has an emitter region and a base region, the base region has a channel portion, and a density in the upper surface of the mesa portion in the region in which the channel portion is projected onto the upper surface of the mesa portion of the boundary portion may be smaller than the density of the region in which the channel portion is projected onto the upper surface of the mesa portion of the transistor portion.

The object of the present invention is to increase the breakdown voltage without thickening an SOI layer in a wafer-bonded dielectric isolated structure. A device region of a SiC-SOI device includes: a first trench continuously or intermittently surrounding an n.sup. type drift region and not penetrating a SiC substrate; an n.sup.+ type side surface diffusion region formed on each side surface of the first trench; an n.sup.+ type bottom diffusion region formed under the n.sup. type drift region and in contact with the n.sup.+ type side surface diffusion region; and a plurality of thin insulating films formed in proximity to a surface of the n.sup. type drift region at regular spacings of 0.4 m or less. A surrounding region includes a second trench formed to continuously surround the first trench and penetrating the SiC substrate, and an isolated insulating film region formed on each side surface of the second trench.

A semiconductor apparatus has a semiconductor substrate, a first trench provided in a front surface of the semiconductor substrate, an anode electrode provided inside the first trench, and a cathode electrode provided on a back surface of the semiconductor substrate. The semiconductor substrate has a first p-type region, a second p-type region, and a main n-type region which is in contact with the first p-type region and the second p-type region, and is in Schottky contact with the anode electrode in the side surface of the first trench. The semiconductor substrate satisfies the relationship that an area of the first trench, when the front surface is viewed in a plan view, is smaller than an area of a Schottky interface where the main n-type region is in contact with the anode electrode in the side surface of the first trench.

Devices, methods and techniques are disclosed to suppress electrical discharge and breakdown in insulating or encapsulation material(s) applied to solid-state devices. In one example aspect, a multi-layer encapsulation film includes a first layer of a first dielectric material and a second layer of a second dielectric material. An interface between the first layer and the second layer is configured to include molecular bonds to prevent charge carriers from crossing between the first layer and the second layer. The multi-layer encapsulation configuration is structured to allow an electrical contact and a substrate of the solid-state device to be at least partially surrounded by the multi-layer encapsulation configuration.

A gallium nitride high electron mobility transistor and a formation method therefor are provided. The transistor includes: a substrate; a gallium nitride channel layer disposed on the substrate; a first barrier layer disposed on the gallium nitride channel layer; a gate, a source and a drain disposed on the first barrier layer, the source and the drain being respectively disposed on two sides of the gate; and a second barrier layer disposed on a surface of the first barrier layer between the gate and the drain, a side wall of the second barrier layer being connected to a side wall on one side of the gate and being configured to generate two-dimensional hole gas. The high electron mobility transistor has a higher breakdown voltage.

The present disclosure relates to semiconductor structures and, more particularly, to extended drain MOSFET structures with a dual oxide thickness and methods of manufacture. The structure includes an extended drain metal oxide semiconductor transistor (EDMOS) comprising a gate structure with a dual oxide scheme.

The present invention discloses a preparation method of a low temperature polysilicon thin film transistor including: successively forming a polysilicon active layer and a gate insulating layer covering the active layer on a base substrate; implanting nitrogen ions on a surface of the polysilicon active layer facing the gate insulating layer by an ion implantation process to form an ion implantation layer; and recrystallizing the ion implantation layer by a high temperature annealing process to form a silicon nitride spacing layer between the polysilicon active layer and the gate insulating layer. The present invention also provides a low temperature polysilicon thin film transistor including a polysilicon active layer, a gate insulating layer, a gate electrode, a source electrode and a drain electrode successively provided on a base substrate, wherein a connection interface between the polysilicon active layer and the gate insulating layer is formed with a silicon nitride spacing layer, and the silicon nitride spacing layer and the polysilicon active layer are in a integrally interconnected structure.

The present invention relates to an LDMOS device and a method for preparing same. When a field plate hole is formed by etching an interlayer dielectric layer, the etching of the field plate hole is stopped on a blocking layer by means of providing the blocking layer between a semiconductor base and the interlayer dielectric layer. Since the blocking layer is provided with at least one layer of an etch stop layer, and steps are formed on the surface of the blocking layer, at least two levels of formed hole field plates are distributed in a step shape, and lower ends of the first level of hole field plates to the nth level of hole field plates are gradually further away from the drift area in the direction from a gate structure to a drain area.

Disclosed are a semiconductor structure and a preparation method thereof. The semiconductor structure includes a substrate, including a first region arranged at the center of the substrate and a second region arranged at the periphery of the first region; and a composite buffer layer arranged on the substrate, including a carbon-containing first buffer layer including at least one set of a first sub-buffer layer and a second sub-buffer layer stacked in layers; therein, a carbon concentration of the first sub-buffer layer arranged at the first region is higher than that arranged at the second region; and a carbon concentration of the second sub-buffer layer arranged at the first region is lower than that at arranged the second region. Therefore, uniformity of the carbon concentration of the composite buffer layer is improved to improve resistivity of the composite buffer layer, so as to increase breakdown voltage and improve device performance.

A Schottky barrier diode 1 includes: a semiconductor substrate made of gallium oxide; a drift layer made of gallium oxide; an anode electrode brought into Schottky contact with an upper surface of the drift layer; and a cathode electrode brought into ohmic contact with a lower surface of the semiconductor substrate. A ring-shaped outer peripheral trench is formed in the upper surface of the drift layer, and the anode electrode is partly filled in the outer peripheral trench. A ring-shaped back surface trench is formed in the lower surface of the semiconductor substrate such that the bottom thereof reaches the drift layer. This limits a current path to the area surrounded by the back surface trench, thereby mitigating electric field concentration in the vicinity of the bottom of the outer peripheral trench.