A power semiconductor device includes a semiconductor layer based on silicon carbide (SiC), a vertical drift region positioned to extend in a vertical direction inside the semiconductor layer and having a first conductive type, a well region positioned in at least one side of the vertical drift region to make contact with the vertical drift region and having a second conductive type, recess gate electrodes extending from a surface of the semiconductor layer into the semiconductor layer and buried in the vertical drift region and the well region to cross the vertical drift region and the well region in a first direction, source regions positioned in the well region between the recess gate electrodes and having the first conductive type, and insulating-layer protective regions surrounding lower portions of the recess gate electrodes, respectively, in the vertical drift region, and having the second conductive type.

A semiconductor device with densified dielectric structures and a method of fabricating the same are disclosed. The method includes forming a fin structure, forming an isolation structure adjacent to the fin structure, forming a source/drain (S/D) region on the fin structure, depositing a flowable dielectric layer on the isolation structure, converting the flowable dielectric layer into a non-flowable dielectric layer, performing a densification process on the non-flowable dielectric layer, and repeating the depositing, converting, and performing to form a stack of densified dielectric layers surrounding the S/D region.

There is disclosed a structure in a wide band gap material such as silicon carbide wherein there is a buried grid and shields covering at least one middle point between two adjacent parts of the buried grid, when viewed from above. Advantages of the invention include easy manufacture without extra lithographic steps compared with standard manufacturing process, an improved trade-off between the current conduction and voltage blocking characteristics of a JBSD comprising the structure.

A semiconductor-on-insulator (e.g., silicon-on-insulator) structure having superior radio frequency device performance, and a method of preparing such a structure, is provided by utilizing a single crystal silicon handle wafer sliced from a float zone grown single crystal silicon ingot.

A device includes a semiconductor substrate, a channel layer, a gate structure, source/drain epitaxial structures, and a dielectric isolation layer. The channel layer is over the semiconductor substrate. The gate structure is over the semiconductor substrate and surrounds the channel layer. The source/drain epitaxial structures are connected to the channel layer and arranged in a first direction. The dielectric isolation layer is between the gate structure and the semiconductor substrate. The dielectric isolation layer is wider than the gate structure but narrower than the channel layer in the first direction.

A semiconductor device is provided that is useful for ESD protection purposes. The device includes a semiconductor die; diode unit cells integrated on the die and being electrically connected between the first and second terminal, each unit cell includes a first region of a first charge type in the die and a second region of a second charge type in the die; an isolation structure arranged in the die, the isolation structure being configured to electrically isolate the unit cells from one another in the semiconductor die; and contacts including first contacts that are electrically connected to the first terminal and second contacts that are electrically connected to the second terminal, and each contact among the first and second contacts is electrically connected to the first region of a respective unit cell among the unit cells and to the second region of another unit cell among the unit cells.

A lateral transistor tile is formed with first and second collector regions that longitudinally span first and second sides of the transistor tile; and a base region and an emitter region that are between the first and second collector regions and are both centered on a longitudinal midline of the transistor tile. A base-collector current, a collector-emitter current, and a base-emitter current flow horizontally; and the direction of the base-emitter current is perpendicular to the direction of the base-collector current and the collector-emitter current. Lateral BJT transistors having a variety of layouts are formed from a plurality of the tiles and share common components thereof.

A device includes a diode that includes a first group III-nitride (III-N) material and a transistor adjacent to the diode, where the transistor includes the first III-N material. The diode includes a second III-N material, a third III-N material between the first III-N material and the second III-N material, a first terminal including a metal in contact with the third III-N material, a second terminal coupled to the first terminal through the first group III-N material. The device further includes a transistor structure, adjacent to the diode structure. The transistor structure includes the first, second, and third III-N materials, a source and drain, a gate electrode and a gate dielectric between the gate electrode and each of the first, second and third III-N materials.

The present disclosure describes a method for the formation of gate stacks having two or more titanium-aluminum (TiAl) layers with different Al concentrations (e.g., different Al/Ti ratios). For example, a gate structure can include a first TiAl layer with a first Al/Ti ratio and a second TiAl layer with a second Al/Ti ratio greater than the first Al/Ti ratio of the first TiAl layer.

A modified structure of an n-channel lateral double-diffused metal oxide semiconductor (LDMOS) transistor is provided to suppress the rupturing of the gate-oxide which can occur during the operation of the LDMOS transistor. The LDMOS transistor comprises a dielectric isolation structure which physically isolates the region comprising a parasitic NPN transistor from the region generating a hole current due to weak-impact ionization, e.g., the extended drain region of the LDMOS transistor. According to an embodiment of the disclosure, this can be achieved using a vertical trench between the two regions. Further embodiments are also proposed to enable a reduction in the gain of the parasitic NPN transistor and in the backgate resistance in order to further improve the robustness of the LDMOS transistor.