Gate-all-around (GAA) devices and methods of manufacturing such devices are described herein. A method includes forming a multi-layer structure over a substrate and forming a plurality of source/drain regions in the multi-layer structure. Fins are then patterned into the multi-layer structure through adjacent source/drain regions. A wire release process is performed to remove materials of one or more of the layers in the multi-layer stack. The remaining layers of the multi-layer stack form a stack of nanostructures connecting adjacent source/drain regions of the fins.

In an embodiment, a device includes: a first fin; a gate structure over the first fin; a first source/drain region adjacent the gate structure; an etch stop layer over the first source/drain region; a conductive line over the etch stop layer, the conductive line isolated from the first source/drain region by the etch stop layer, a top surface of the conductive line being coplanar with a top surface of the gate structure; and a power rail contact extending through the first fin, the power rail contact connected to the first source/drain region.

A device includes a substrate and a gate structure wrapping around at least one vertical stack of nanostructure channels. The device includes a source/drain region abutting the gate structure, and a source/drain contact over the source/drain region. The device includes an etch stop layer laterally between the source/drain contact and the gate structure and having a first sidewall in contact with the source/drain contact, and a second sidewall opposite the first sidewall. The device includes a source/drain contact isolation structure embedded in the source/drain contact and having a third sidewall substantially coplanar with the second sidewall of the etch stop layer.

A semiconductor device, includes a device layer comprising: a channel region; a gate stack over and along sidewalls of the channel region and a first insulating fin; and an epitaxial source/drain region adjacent the channel region, wherein the epitaxial source/drain region extends through the first insulating fin. The semiconductor device further includes a front-side interconnect structure on a first side of the device layer; and a backside interconnect structure on a second side of the device layer opposite the first side of the device layer. The backside interconnect structure comprises a backside source/drain contact that is electrically connected to the epitaxial source/drain region.

According to one example, a method includes performing a first etching process on a fin stack to form a first recess and a second recess at a first depth, the first recess and the second recess on opposite sides of a gate structure that is on the fin stack. The method further includes depositing inner spacers within the first recess and the second recess. The method further includes, after depositing the inner spacers, performing a second etching process to extend a depth of the first recess to a second depth. The method further includes forming a dummy contact region within the first recess, forming a source structure within the first recess on the dummy contact region, and forming a drain structure within the second recess.

Semiconductor devices having improved heat dissipation and methods of forming the same are disclosed. In an embodiment, a device includes a first transistor structure; a front-side interconnect structure on a front-side of the first transistor structure, the front-side interconnect structure including front-side conductive lines; a backside interconnect structure on a backside of the first transistor structure, the backside interconnect structure including backside conductive lines, the backside conductive lines having line widths greater than line widths of the front-side conductive lines; and a first heat dissipation substrate coupled to the backside interconnect structure.

A semiconductor structure includes a two-dimensional array of unit cell structures overlying a substrate. Each unit cell structure includes an active layer, a gate dielectric underlying the active layer, two gate electrodes underlying the gate dielectric, and two source electrodes and a drain electrode overlying the active layer. Word lines underlie the active layers. Each unit cell structure includes portions of a respective set of four word lines, which includes two word lines that are electrically connected to two electrodes in the unit cell structure and two additional word lines that are electrically isolated from the two electrodes in the unit cell structure.

A semiconductor device includes a substrate including an active pattern, a channel pattern and a source/drain pattern on the active pattern, a gate electrode provided on the channel pattern and extended in a first direction, and an active contact coupled to the source/drain pattern. The active contact includes a buried portion buried in the source/drain pattern and a contact portion on the buried portion. The buried portion includes an expansion portion provided in a lower portion of the source/drain pattern and a vertical extension portion connecting the contact portion to the expansion portion.

It is an object of the present invention to connect a wiring, an electrode, or the like formed with two incompatible films (an ITO film and an aluminum film) without increasing the cross-sectional area of the wiring and to achieve lower power consumption even when the screen size becomes larger. The present invention provides a two-layer structure including an upper layer and a lower layer having a larger width than the upper layer. A first conductive layer is formed with Ti or Mo, and a second conductive layer is formed with aluminum (pure aluminum) having low electric resistance over the first conductive layer. A part of the lower layer projected from the end section of the upper layer is bonded with ITO.

Semiconductor devices and methods for forming the semiconductor devices include forming a sacrificial layer on a substrate on each side of a stack of nanosheets, the stack of nanosheets including first nanosheets and second nanosheets stacked in alternating fashion with a dummy gate structure formed thereon. Source and drain regions are grown on from the sacrificial layer and from ends of the second nanosheets to form source and drain regions in contact with each side of the stack of nanosheets. The sacrificial layer is removed. An interlevel dielectric is deposited around the source and drain regions to fill between the source and drain regions and the substrate.