The present disclosure provides a semiconductor structure. The semiconductor structure includes a substrate; and a seal ring region enclosing a circuit region disposed over the substrate. The seal ring region further includes a fin ring protruding from the substrate having a first width; an isolation ring disposed over the substrate and adjacent to the fin ring; a gate ring disposed over the fin ring having a second width, wherein the second width is less than the first width; an epitaxial ring disposed between the fin ring and the isolation ring; and a contact ring lands on the epitaxial ring and the isolation ring. Each of the fin ring, the isolation ring, the epitaxial ring, and the contact ring extends parallel to each other and fully surrounds the circuit region to form a closed loop.

A method for fabricating an array substrate, the array substrate, and a thin film transistor are provided. The thin film transistor includes a gate electrode, an active layer, a source electrode, a drain electrode, and an interlayer insulating layer. The active layer is disposed corresponding to the gate electrode. The source electrode and the drain electrode are disposed at both sides of the active layer and electrically connected to the active layer. The interlayer insulating layer is disposed between the active layer and the source electrode, and between the active layer and the drain electrode. The interlayer insulating layer is provided with step-shaped contact holes. The source electrode and the drain electrode are filled in the contact holes and electrically connected to the active layer.

An electronic device includes a substrate, a plurality of transistors and a plurality of drain contact holes. The transistors are disposed on the substrate. Each transistor has a semiconductor, a source and a drain. The drains are electrically connected to the semiconductors through the drain contact holes. A number of the drain contact holes is less than a number of the drains. The electronic device of the embodiment of the disclosure has better reliability or better display quality.

Methods, transistors, and systems are discussed related to anisotropically etching back deposited epitaxial source and drain semiconductor materials for reduced lateral source and drain spans in the fabricated transistors. Such lateral width reduction of the source and drain materials enables improved transistor scaling and perturbation reduction in the resultant source and drain semiconductor materials.

Described herein are integrated circuit devices with metal-oxide semiconductor channels and carbon source and drain (S/D) contacts. S/D contacts conduct current to and from the semiconductor devices, e.g., to the source and drain regions of a transistor. Carbon S/D contacts may be particularly useful with semiconductor devices that use certain channel materials, such as indium gallium zinc oxide.

A semiconductor device includes an active region extending on a substrate in a first direction, a gate electrode intersecting the active region and extending in a second direction, perpendicular to the first direction, a contact structure disposed on the active region on one side of the gate electrode and extending in the second direction, and a first via disposed on the contact structure to be connected to the contact structure and has a shape in which a length in the second direction is greater than a length in the first direction. A plurality of first metal interconnections are provided, which extend in the first direction on the first via, and are connected to the first via. A second via is provided, which is disposed on the plurality of first metal interconnections to be connected to the plurality of first metal interconnections and has a shape in which a length in the second direction is greater than a length in the first direction.

Described herein are integrated circuit devices with lined interconnects. Interconnect liners can help maintain conductivity between semiconductor devices (e.g., transistors) and the interconnects that conduct current to and from the semiconductor devices. In some embodiments, metal interconnects are lined with a tungsten liner. Tungsten liners may be particularly useful with semiconductor devices that use certain channel materials, such as indium gallium zinc oxide.

A semiconductor structure includes a substrate; bottom dielectric isolation (BDI) on the substrate; a first source/drain region on the BDI; and a nanosheet stack on the BDI. The nanosheet stack includes gate stack layers; semiconductor nanosheets interleaved with the gate stack layers and contacting the first source/drain region; and first inner spacers adjacent to the first source/drain region and separating the first source/drain region from the gate stack layers. The structure also includes a second source/drain region contacting the semiconductor nanosheet and extending from the top of the nanosheet stack down through the BDI to the substrate. Accordingly, the nanosheet stack also includes second inner spacers in the nanosheet stack adjacent to the second source/drain region and separating the second source/drain region from the gate stack layers.

Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment, a semiconductor device comprises a sheet that is a semiconductor. In an embodiment a length dimension of the sheet and a width dimension of the sheet are greater than a thickness dimension of the sheet. In an embodiment, a gate structure is around the sheet, and a first spacer is adjacent to a first end of the gate structure, and a second spacer adjacent to a second end of the gate structure. In an embodiment, a source contact is around the sheet and adjacent to the first spacer, and a drain contact is around the sheet and adjacent to the second spacer.

Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment, a semiconductor device comprises a first transistor on a first level, and a second transistor on a second level above the first level. In an embodiment, an insulating layer is between the first level and the second level, and a via passes through the insulating layer, and electrically couples the first transistor to the second transistor. In an embodiment, the first transistor and the second transistor comprise a first channel, and a second channel over the first channel. In an embodiment, the first second transistor further comprise a gate structure between the first channel and the second channel, a source contact on a first end of the first channel and the second channel, and a drain contact on a second end of the first channel and the second channel.