A method includes forming a plurality of first semiconductor layers and a plurality of second semiconductor layers in an alternate manner over a substrate; patterning the first and second semiconductor layers and the substrate to form a fin structure, in which the fin structure includes a base portion protruding from the substrate and remaining portions of the first and second semiconductor layers; etching the fin structure to form a first recess extending through the remaining portions of the first and second semiconductor layers and into the base portion; epitaxially growing a first epitaxy layer in the first recess; epitaxially growing a second epitaxy layer over the first epitaxy layer; oxidizing the first epitaxy layer, wherein the second epitaxy layer remains unoxidized after the first epitaxy layer is oxidized; and after oxidizing the first epitaxy layer, forming a source/drain epitaxy structure on the second epitaxy layer.

A semiconductor structure comprises a substrate defining a first axis and a second axis in orthogonal relation to the first axis, first and second nanosheet stacks disposed on the substrate, a gate structure on each of the first and second nanosheet stacks, a source/drain region adjacent each of the first and second nanosheet stacks, a wrap-around contact disposed about each source/drain region and an isolator pillar disposed between the wrap-around contacts.

Semiconductor structure and forming method thereof are provided. The forming method includes: providing a substrate; forming a plurality of initial composite layers on a portion of the substrate; forming a plurality of source and drain layers on surfaces of the plurality of channel layers exposed by a first opening and grooves by using a selective epitaxial growth process, the plurality of source and drain layers being parallel to a first direction and distributed along a second direction, the second direction being parallel to a normal direction of the substrate, and gaps being between adjacent source and drain layers; forming contact layers on surfaces of the plurality of source and drain layers and in the gaps; and forming a conductive structure on a surface of a contact layer on a source and drain layer of the plurality of source and drain layers.

There is provided a semiconductor device capable of improving the performance and reliability of a device. The semiconductor device including an active pattern extending in a first direction, a gate structure on the active pattern, the gate structure extending in a second direction different from the first direction and including a gate insulating layer and a gate filling layer, a gate spacer extending in the second direction, on a sidewall of the gate structure, a gate shield insulating pattern on a sidewall of the gate spacer, covering an upper surface of the gate insulating layer, and including an insulating material, and a gate capping pattern covering an upper surface of the gate filling layer, on the gate structure may be provided.

An inner sidewall spacer is formed before the formation of the epitaxial source/drain features and an outer sidewall spacer is formed after the epitaxial source/drain features. The two-level sidewall spacer design increases volume of the epitaxial source/drain features, thus improving ion performance. The thicker sidewall spacers also reduce capacitance between source/drain contacts and the gate electrode. In some embodiments, semiconductor nanosheets may be etched to reduce thickness prior to forming replacement gate structures. Nanosheets with reduced thickness improve device swing performance, reduce DIBL effect without sacrificing the channel resistance and epitaxial growth margin.

A semiconductor structure is provided. The semiconductor structure includes a first gate stack wrapping around first nanostructures, a second gate stack wrapping around second nanostructures, a gate isolation structure interposing between the first gate stack and the second gate stack, a first source/drain feature adjoining the first nanostructures, a second source/drain feature adjoining the second nanostructures, and a source/drain spacer structure interposing between the first source/drain feature and the second source/drain feature. The gate isolation structure covers a sidewall of the source/drain spacer structure.

A device includes a substrate having a top surface, a fin extending lengthwise along a first direction, a source feature and a drain feature, a gate structure having a gate stack extending along a second direction perpendicular to the first direction and interposing between the source and drain features, a gate via directly disposed on the gate stack, a source via electrically connecting the source feature, and a drain via electrically connecting the drain feature. The fin includes a stack of channel layers engaged by the gate stack. The source via has a first dimension along the second direction and a second dimension along the first direction, the drain via feature has a third dimension along the second direction and a fourth dimension along the first direction. A ratio of the first dimension to the second dimension is greater than a ratio of the third dimension to the fourth dimension.

A method of forming a semiconductor structure includes following operations. A memory layer is formed over the first gate electrode. A channel layer is formed over the memory layer. A first SUT treatment is performed. A second dielectric layer is formed over the memory layer and the channel layer. A source electrode and a drain electrode are formed in the second dielectric layer. A temperature of the first SUT treatment is less than approximately 400° C.

A semiconductor device includes an active region that extends in a first horizontal direction. A source/drain component is disposed over the active region. A source/drain contact is disposed over the source/drain component. A gate structure is disposed over the active region. The gate structure extends in a second horizontal direction different from the first horizontal direction. Side surfaces of the source/drain contact are substantially more tapered in the second horizontal direction than in the first horizontal direction.

A semiconductor device with C-shaped channel portion and an electronic apparatus including the semiconductor device are disclosed. According to the embodiments, the semiconductor device may include a first semiconductor element and a second semiconductor element adjacent in a first direction. The first semiconductor element and the second semiconductor element may respectively include: a channel portion on a substrate, the channel portion including a curved nano-sheet or nano-wire with a C-shaped section; source/drain portions at upper and lower ends of the channel portion with respect to the substrate, respectively; and a gate stack surrounding a periphery of the channel portion. The channel portion of the first semiconductor element and the channel portion of the second semiconductor element may be substantially coplanar.