A semiconductor structure is provided that includes a second nanosheet device of a second conductivity type stacked over a first nanosheet device of a first conductivity type that is different from the second conductivity type. Each of the first and second nanosheet devices includes at least one semiconductor channel material nanosheet. One side of the least one semiconductor channel material nanosheet of both the first and second nanosheet devices contacts a dielectric material, while another side of the least one semiconductor channel material nanosheet of both the first and second nanosheet devices contacts a functional gate-containing liner that extends laterally to connect to a gate contact of each first and second nanosheet device.

A semiconductor device includes an active region extending on a substrate in a first direction, a gate structure including a gate electrode extending on the substrate in a second direction and traversing the active region, a spacer structure extending on opposing sidewalls of the gate electrode in the second direction, and a capping layer on the gate electrode and the spacer structure, a source/drain region on the active region adjacent the gate structure, and a first contact plug connected to the source/drain region and a second contact plug connected to the gate structure. The capping layer includes a lower capping layer and an upper capping layer on the lower capping layer, and the second contact plug penetrates through the capping layer, is connected to the gate electrode and includes a convex sidewall penetrating into the upper capping layer.

A semiconductor device includes an oxide semiconductor layer, disposed over a substrate. A source electrode of a metal nitride is disposed on the oxide semiconductor layer. A drain electrode of the metal nitride is disposed on the oxide semiconductor layer. A metal-nitride oxidation layer is formed on a surface of the source electrode and the drain electrode. A ratio of a thickness of the metal-nitride oxidation layer to a thickness of the drain electrode or the source electrode is equal to or less than 0.2.

A transistor is described. The transistor includes a substrate, a first semiconductor structure above the substrate, a second semiconductor structure above the substrate, a source contact that includes a first metal structure that contacts a plurality of surfaces of the first semiconductor structure and a drain contact that includes a second metal structure that contacts a plurality of surfaces of the second semiconductor structure. The transistor also includes a gate below a back side of the substrate.

A display panel includes a base, at least one separation pillar, at least one protection pattern, and a light-emitting functional layer. The at least one separation pillar is disposed in the isolation region on the base, each separation pillar is disposed around the opening region, and a longitudinal section of the separation pillar perpendicular to an extending direction of the separation pillar is I-shaped. The at least one protection pattern is disposed on a surface of at least one separation pillar facing away from the base. The light-emitting functional layer is disposed at least in both the pixel region and the isolation region on a surface of the at least one protection pattern facing away from the base, wherein the light-emitting functional layer is disconnected at an inner side face and an outer side face of the separation pillar.

An integrated circuit device includes a metal film and a complex capping layer covering a top surface of the metal film. The metal film includes a first metal, and penetrates at least a portion of an insulating film formed over a substrate. The complex capping layer includes a conductive alloy capping layer covering the top surface of the metal film, and an insulating capping layer covering a top surface of the conductive alloy capping layer and a top surface of the insulating film. The conductive alloy capping layer includes a semiconductor element and a second metal different from the first metal. The insulating capping layer includes a third metal.

A semiconductor device is provided. The semiconductor device includes a semiconductor fin over a substrate, and a gate structure along sidewalls and the top surface of the semiconductor fin. The gate structure covers the first portion of the semiconductor fin. The semiconductor device also includes a source/drain feature adjacent to the gate structure. The semiconductor device further includes a source/drain contact connected to the source/drain feature. The source/drain contact extends downwards to a position that is lower than the top surface of the first portion of the semiconductor fin.

An electronic device comprises a panel, a driving circuit configured to drive the panel, and a transistor disposed in the panel. The transistor includes a first insulation film on a substrate, an active layer disposed on the first insulation film, a second insulation film disposed on the active layer and the first insulation film to cover the active layer, the second insulation film having a thickness smaller than a thickness of the first insulation film, a source electrode disposed on the second insulation film and spaced apart from the active layer by the second insulation film, the source electrode overlapping an end of the active layer, and a drain electrode disposed on the second insulation film and spaced apart from the active layer by the second insulation film, the drain electrode overlapping another end of the active layer.

According to one embodiment, a display device includes a display panel and a drive circuit. A transistor provided in a pixel portion or a peripheral portion of the display panel includes a semiconductor layer having a first end and a second end, first and second gate electrodes overlapping the semiconductor layer, a source electrode connected to the first end, and a drain electrode connected to the second end. The first and second gate electrodes are disposed in a first layer. The source electrode and the drain electrode are disposed in a second layer. The source electrode is formed to cover at least a first channel region in planar view. The drain electrode is formed to cover at least a second channel region in planar view.

An active matrix substrate includes a plurality of gate bus lines, a plurality of source bus lines located closer to the substrate side; a lower insulating layer that covers the source bus lines; an interlayer insulating layer that covers the gate bus lines; a plurality of oxide semiconductor TFTs disposed in association with respective pixel regions; a pixel electrode disposed in each of the pixel regions; and a plurality of source contact portions each of which electrically connects one of the oxide semiconductor TFTs to the corresponding one of the source bus lines, in which each of the oxide semiconductor TFTs includes an oxide semiconductor layer disposed on the lower insulating layer, a gate electrode disposed on a portion of the oxide semiconductor layer, and a source electrode formed of a conductive film, and each of the source contact portions includes a source contact hole, and a connection electrode.