A thin film transistor substrate includes a data line, a gate line, a gate electrode, a source electrode, a first drain electrode, a semiconductor layer and a second drain electrode. The data line and the gate line cross each other on a base substrate. The gate electrode is electrically connected to the gate line. The source electrode is electrically connected to the data line. The first drain electrode and the source electrode face each other. The semiconductor layer serves as a channel between the source electrode and the first drain electrode. The second drain electrode is disposed on the first drain electrode. The second drain electrode is electrically connected to the first drain electrode.

According to one embodiment, a semiconductor device includes contact holes passing through a source region of a drain region of an interlayer insulating film and oxide semiconductor layer to reach an insulating substrate, wherein a source electrode and a drain electrode are formed inside the contact holes, respectively.

Provided is a display control element which can improve a display device in driving speed. A display control element (A) includes a semiconductor layer (l) having a counter surface (p) connected to a gate line (GL), a source electrode (s) provided on a side of the semiconductor layer (l) and connected to a source line (SL), and drain electrodes (da and db) provided on the side of the semiconductor layer (l) and connected to the same pixel (P). The gate surface, the source electrode (s), and each of the drain electrodes constitute a single thin film transistor.

A liquid-crystal display including: a gate line extending in a first direction; a gate electrode protruding from the gate line; a gate insulating layer arranged on the gate electrode; an active layer arranged on the gate insulating layer while being insulated from the gate electrode; a data line arranged on the active layer and extending in a second direction; a source electrode protruding from the data line, having a portion overlapping the gate electrode on a plane, and including a plurality of source electrode branches that are separate from each other; a drain electrode being separate from the source electrode, and including a plurality of drain electrode branches, each being arranged between two of the plurality of source electrode branches, and a drain electrode connecting part connecting the plurality of drain electrode branches; a pixel electrode defining a pixel region; a liquid-crystal layer arranged on the pixel electrode.

The present disclosure relates to semiconductor structures and, more particularly, to a layout optimization for radio frequency (RF) device performance and methods of manufacture. The structure includes: a first active device on a substrate; source and drain diffusion regions adjacent to the first active device; and a first contact in electrical contact with the source and drain diffusion regions and which is spaced away from the first active device to optimize a stress component in a channel region of the first active device.

A transistor is described. The transistor includes a substrate, a first semiconductor structure above the substrate, a second semiconductor structure above the substrate, a source contact that includes a first metal structure that contacts a plurality of surfaces of the first semiconductor structure and a drain contact that includes a second metal structure that contacts a plurality of surfaces of the second semiconductor structure. The transistor also includes a gate below a back side of the substrate.

A transistor includes an oxide semiconductor layer, a source electrode and a drain electrode disposed spaced apart from each other on the oxide semiconductor layer, a gate electrode spaced apart from the oxide semiconductor layer, a gate insulating layer disposed between the oxide semiconductor layer and the gate electrode, and a graphene layer disposed between the gate electrode and the gate insulating layer and doped with a metal.

Embodiments herein describe techniques for a semiconductor device including a memory cell vertically above a substrate. The memory cell includes a metal-insulator-metal (MIM) capacitor at a lower device portion, and a transistor at an upper device portion above the lower device portion. The MIM capacitor includes a first plate, and a second plate separated from the first plate by a capacitor dielectric layer. The first plate includes a first group of metal contacts coupled to a metal electrode vertically above the substrate. The first group of metal contacts are within one or more metal layers above the substrate in a horizontal direction in parallel to a surface of the substrate. Furthermore, the metal electrode of the first plate of the MIM capacitor is also a source electrode of the transistor. Other embodiments may be described and/or claimed.

A resistor includes a substrate including an active region protruding from an upper surface of the substrate and extending in a first horizontal direction, a doped region extending in the first horizontal direction on the active region and comprising a semiconductor layer with n-type impurities, a plurality of channel layers spaced apart from each other in a vertical direction on the active region and connected to the doped region, a first gate electrode and a second gate electrode extending in the second horizontal direction intersecting the first horizontal direction and surrounding the plurality of channel layers, a first contact plug and a second contact plug in contact with an upper surface of the doped region. The first contact plug is adjacent to the first gate electrode. The second contact plug is adjacent to the second gate electrode.

It is an object to provide a highly reliable semiconductor device including a thin film transistor with stable electric characteristics. In a semiconductor device including an inverted staggered thin film transistor whose semiconductor layer is an oxide semiconductor layer, a buffer layer is provided over the oxide semiconductor layer. The buffer layer is in contact with a channel formation region of the semiconductor layer and source and drain electrode layers. A film of the buffer layer has resistance distribution. A region provided over the channel formation region of the semiconductor layer has lower electrical conductivity than the channel formation region of the semiconductor layer, and a region in contact with the source and drain electrode layers has higher electrical conductivity than the channel formation region of the semiconductor layer.