Embodiments of the disclosure relate to a display panel and a display device. Specifically, there may be provided a display panel and display device capable of simplifying the process, by comprising a substrate, first to fourth signal lines and an active layer disposed on the substrate, a first metal layer and a second metal layer disposed on a portion of an upper surface of the active layer and spaced apart from each other, a first insulation film disposed on the first and second metal layers, a second insulation film disposed on the first insulation film, an electrode pattern disposed on the active layer and the first insulation film and not overlapping the second insulation film, and a fifth signal line disposed on the second insulation film and crossing the first to fourth signal lines spaced apart from each other, wherein the first electrode contacts an upper surface of the first metal layer disposed on the active layer, and wherein the fifth signal line is disposed on the same layer as the first electrode.

Embodiments of the disclosure relate to a thin film transistor array substrate and an electronic device including the same. Specifically, there may be provided a thin film transistor array substrate and an electronic device including the same, which may have high current characteristics in a small area, by including a first electrode, a first insulation film including a hole exposing a portion of an upper surface of the first electrode, an active layer contacting a portion of an upper surface of the first insulation film and the portion of the upper surface of the first electrode, a second insulation film disposed on the active layer, a gate electrode disposed on the second insulation film, a third insulation film disposed on the gate electrode, and a second electrode and a third electrode disposed on the third insulation film, spaced apart from each other, and electrically connected with the active layer, wherein the same signal is applied to the second electrode and the third electrode, wherein the active layer includes a first channel area and a second channel area spaced apart from each other, and wherein the first channel area and the second channel area include an area positioned on a side surface of the hole of the first insulation film.

A thin film transistor and a display panel having the same are provided. A display panel includes a substrate, an active layer disposed over the substrate and including a source region, a drain region, and a middle region between the source region and the drain region, and a gate electrode over the active layer and disposed overlapping with the middle region, and the active layer includes a plurality of holes disposed symmetrically with respect to the middle region. The display panel can improve its reliability owing to heat dissipation paths through the plurality of holes.

A semiconductor device includes a substrate that includes an active pattern, a channel pattern and a source/drain pattern on the active pattern, a gate electrode on the channel pattern, an active contact electrically connected to the source/drain pattern, and a gate contact electrically connected to the gate electrode. The active contact includes a first barrier pattern, a first seed pattern on the first barrier pattern, a first fill pattern on the first seed pattern, and a first metal-containing pattern between the first seed pattern and the first fill pattern. The first metal-containing pattern includes tungsten nitride. A nitrogen concentration of the first metal-containing pattern decreases in a direction toward the substrate.

A via connection layer for an electronic package and method for fabricating a via connection layer are provided. The via connection layer includes asymmetric via(s) formed in the via connection layer. The asymmetric via include a first sidewall with a first slope angle in a first direction and a second sidewall, where the second sidewall includes a second slope angle in the first direction.

The reliability of a transistor including an oxide semiconductor can be improved by suppressing a change in electrical characteristics. A transistor included in a semiconductor device includes a first oxide semiconductor film over a first insulating film, a gate insulating film over the first oxide semiconductor film, a second oxide semiconductor film over the gate insulating film, and a second insulating film over the first oxide semiconductor film and the second oxide semiconductor film. The first oxide semiconductor film includes a channel region in contact with the gate insulating film, a source region in contact with the second insulating film, and a drain region in contact with the second insulating film. The second oxide semiconductor film has a higher carrier density than the first oxide semiconductor film.

A first transistor, a second transistor, a capacitor, and first to third conductors are included. The first transistor includes a first gate, a source, and a drain. The second transistor includes a second gate, a third gate over the second gate, first and second low-resistance regions, and an oxide sandwiched between the second gate and the third gate. The capacitor includes a first electrode, a second electrode, and an insulator sandwiched therebetween. The first low-resistance region overlaps with the first gate. The first conductor is electrically connected to the first gate and is connected to a bottom surface of the first low-resistance region. The capacitor overlaps with the first low-resistance region. The second conductor is electrically connected to the drain. The third conductor overlaps with the second conductor and is connected to the second conductor and a side surface of the second low-resistance region.

The present disclosure provides a semiconductor device that includes a semiconductor fin disposed over a substrate, an isolation structure at least partially surrounding the fin, an epitaxial source/drain (S/D) feature disposed over the semiconductor fin, where an extended portion of the epitaxial S/D feature extends over the isolation structure, and a silicide layer disposed on the epitaxial S/D feature, where the silicide layer covers top, bottom, sidewall, front, and back surfaces of the extended portion of the S/D feature.

A semiconductor memory device includes: a substrate having a first channel structure and a second channel structure respectively extending in a first direction and arranged in a second direction perpendicular to the first direction; a first gate structure disposed on the first channel structure and extending in the second direction on the substrate; a second gate structure disposed on the second channel structure and extending in the second direction; first source/drain regions respectively disposed on opposite sides of the first gate structure; second source/drain regions respectively disposed on opposite sides of the second gate structure; a gate separation pattern disposed between the first and second gate structures and having an upper surface at a level lower than that of an upper surface of each of the first and second gate structures, the gate separation pattern including a first insulating material; and a gate capping layer disposed on the first and second gate structures and having an extension portion extending between the first and second gate structures to be connected to the gate separation pattern, the gate capping layer including a second insulating material different from the first insulating material.

An electro-optical device includes a scanning line extending along a first direction and having a light shielding property, a transistor having a semiconductor layer extending along the first direction so as to overlap with the scanning line, a contact hole electrically coupled to the scanning line at a side of a channel region of the semiconductor layer, and an opening provided at a side of a first LDD region and a second LDD region of the semiconductor layer.