A method for forming a memory device is provided. The memory device includes a substrate; a stack including a plurality of conductive layers and a plurality of insulating layers being alternatively stacked on the substrate; a plurality of memory structures formed on the substrate and penetrating the stack; a plurality of isolation structures formed on the substrate and penetrating the stack, wherein the isolation structures dividing the memory structures into a plurality of first memory structures and a plurality of second memory structures; and a plurality of common source pillars formed on the substrate and penetrating the stack, wherein the common source pillars directly contact the isolation structures.

A semiconductor device is proposed. The semiconductor device includes a semiconductor body including a first main surface. A plurality of trench electrode structures extend in parallel along a first lateral direction. A first one of the plurality of trench electrode structures includes a gate electrode. A gate contact is electrically connected to the gate electrode in a gate contact area. The gate contact area is arranged in a first section along the first lateral direction. An isolation structure is arranged between the gate contact and the semiconductor body in the gate contact area. A bottom side of the isolation structure is arranged between a bottom side of the first one of the plurality of trench electrode structures and the first main surface along a vertical direction. The gate contact extends up to or below the first main surface along the vertical direction.

A semiconductor device includes a chip and an electrode that has a laminated structure including a Ti film, a TiN film, a TiAl alloy film and an Al-based metal film that are laminated in that order from the chip side.

A semiconductor device includes a semiconductor substrate and an electrode. The electrode is electrically connected to the semiconductor substrate and located on the semiconductor substrate. The electrode has a lower metal layer, an upper metal layer and an intermediate layer. The lower metal layer is located at a side closer to the semiconductor substrate. The upper metal layer is located above the lower metal layer. The intermediate layer is located between the lower metal layer and the upper metal layer. Each of the lower metal layer and the upper metal layer is made of aluminum or an aluminum alloy. In the aluminum alloy, an element is added to aluminum. The intermediate layer is made of material that is more difficult to react with a hydroxyl group than the lower metal layer and the upper metal layer.

A silicon carbide power semiconductor device is provided, including a substrate, a drift region, a body region, a source region, a base region, a shielding region, a JFET region, a gate structure, an insulating layer, and a source metal layer. The source contacting window has first edges within second edges of the body region corresponding to the first edges, and the source metal layer abuts only a part of the source region. The area of the silicon carbide power semiconductor device of the present disclosure is thus reduced. Therefore, the ratio of the channel length to the area of the silicon carbide power semiconductor device and the ratio of the area of the JFET region to the area of the silicon carbide power semiconductor device are increased, whereby the specific on-resistance of the silicon carbide power semiconductor device is reduced.

Power semiconductor devices comprise a silicon carbide based semiconductor layer structure including an active region defined therein and a gate bond pad that is on the semiconductor layer structure and vertically overlaps the active region.

The present disclosure provides a trench field effect transistor structure and a manufacturing method thereof. The manufacturing method includes: providing a substrate (100), forming an epitaxial layer (101), forming a device trench (102) in the epitaxial layer, and forming a shielding dielectric layer (107), a shielding gate layer (105), a first isolation dielectric layer (108), a gate dielectric layer (109), a gate layer (110), a second isolation dielectric layer (112), a body region (114), a source (115), a source contact hole (118), a source electrode structure (122), and a drain electrode structure (123). During manufacturing of a trench field effect transistor structure, a self-alignment process is adopted in a manufacturing process, so that a cell pitch is not limited by an exposure capability and alignment accuracy of a lithography machine, to further reduce the cell pitch of the device, improve a cell density, and reduce a device channel resistance.

A parallel structure comprising source/drain and channel layers alternately stacked on a substrate, and gate stacks formed around peripheries of the channel layers. Each of the channel layers, the source/drain layers on upper and lower sides of the channel layer, and the gate stack formed around the channel layer, form a semiconductor device. In each semiconductor device, one of the source/drain layers is in contact with a first electrically-conductive channel disposed on an outer periphery of the active region, the other is in contact with a second electrically-conductive channel on the outer periphery of the active region, and the gate stack is in contact with a third electrically-conductive channel disposed on the outer periphery of the active region. The first electrically-conductive channel is common to the semiconductor devices, the second electrically-conductive channel is common to the semiconductor devices, and the third electronically-conductive channel is common to the semiconductor devices.

Aspects of the present technology are directed toward Integrated Circuits (IC) including a plurality of trenches disposed in a substrate about a set of silicide regions. The trenches can extend down into the substrate below the set of silicide regions. The silicide regions can be formed by implanting metal ions into portions of a substrate exposed by a mask layer with narrow pitch openings. The trenches can be formed by selectively etching the substrate utilizing the set of silicide regions as a trench mask. An semiconductor material with various degree of crystallinity can be grown from the silicide regions, in openings that extend through subsequently formed layers down to the silicide regions.

A CFET includes a fin that has a bottom channel portion, a top channel portion, and a channel isolator between the bottom channel portion and the top channel portion. The CFET further includes a source and drain stack that has a bottom source or drain (S/D) region connected to the bottom channel portion, a top S/D region connected to the top channel portion, a source-drain isolator between the bottom S/D region and the top S/D region. The CFET further includes a spacer foot physically connected to a base sidewall portion of the bottom S/D region and a buried S/D contact that is physically connected to an upper sidewall portion of the bottom S/D region. The CFET may further include a common gate around the bottom channel portion, around the top channel portion, and around the channel isolator.