A wide gap semiconductor device has: a drift layer 12 using wide gap semiconductor material being a first conductivity type; a plurality of well regions 20 being a second conductivity type and formed in the drift layer 12; a polysilicon layer 150 provided on the well regions 20 and on the drift layer 12 between the well regions 20; an interlayer insulating film 65 provided on the polysilicon layer 150; a gate pad 120 provided on the interlayer insulating film 65; and a source pad 110 electrically connected to the polysilicon layer 150.

A Metal Oxide Semiconductor (MOS) trench cell includes a plurality of main gate trenches etched in the semiconductor body. In conduction state, the main gate electrode forms vertical MOS channels on the short edges and at least on a portion of the long edges in a mesa of the semiconductor body between neighbouring trenches. The longitudinal direction of the main gate trenches is oriented at an angle between 45 degrees to 90 degrees compared to the longitudinal direction of the first main electrode contacts, in a top plane view. This design offers a wide range of advantages both in terms of performance (reduced losses, improved controllability and reliability) and processability (narrow mesa design rules) and can be applied to both IGBTs and MOSFETs based on silicon or wide bandgap materials such as silicon carbide SiC, zinc oxide (ZnO), gallium oxide (Ga2O3), gallium nitride (GaN), diamond.

A semiconductor device is manufactured by implanting impurity ions in one surface of a semiconductor substrate made of silicon carbide; irradiating a region of the semiconductor substrate implanted with the impurity ions with laser light of a wavelength in the ultraviolet region; and forming, on a surface of a high-concentration impurity layer formed by irradiating with the laser light, an electrode made of metal in ohmic contact with the high-concentration impurity layer. When irradiating with the laser light, a first concentration peak of the impurity ions that exceeds a solubility limit concentration of the impurity ions in silicon carbide is formed in a surface region near the one surface of the semiconductor substrate within the high-concentration impurity layer.

A semiconductor device includes a semiconductor layer having a first surface and a second surface, a first region of a first conductivity type formed on the first surface side of the semiconductor layer, a second region of a second conductivity type in contact with the first region, a third region of the first conductivity type that is in contact with the second region and exposed from the first surface side of the semiconductor layer, a gate electrode facing the second region through a gate insulating film, a first electrode that is physically separated from the gate electrode and faces the second region and the third region through an insulating film, a second electrode formed on the semiconductor layer and electrically connected to the first region, the second region, and the first electrode, and a third electrode electrically connected to the third region.

A semiconductor device of an embodiment includes: a first trench in a silicon carbide layer and extending in a first direction; a second trench and a third trench located in a second direction orthogonal to the first direction with respect to the first trench and adjacent to each other in the first direction, n type first silicon carbide region, p type second silicon carbide region on the first silicon carbide region, n type third silicon carbide region on the second silicon carbide region, p type fourth silicon carbide region between the first silicon carbide region and the second trench, and p type fifth silicon carbide region located between the first silicon carbide region and the third trench; a gate electrode in the first trench; a first electrode; and a second electrode. A part of the first silicon carbide region is located between the second trench and the third trench.

A silicon carbide semiconductor device, including a semiconductor substrate having first and second semiconductor regions and a plurality of third semiconductor regions sequentially formed therein, a plurality of trenches penetrating the second and third semiconductor regions, a plurality of gate electrodes provided in the trenches via a gate insulating film, an interlayer insulating film covering the gate electrodes, a plurality of contact holes penetrating the interlayer insulating film, a first electrode provided in the contact holes and at the surface of the interlayer insulating film, and a second electrode electrically connected to the first semiconductor region. The interlayer insulating film has a plurality of recessed parts and protruding parts, to thereby form at least three recesses and protrusions repeatedly at a surface of the interlayer insulating film. The first electrode includes first to third electrode films, the second electrode film having a shape reflecting the surface of the interlayer insulating film.

Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure, the method includes forming a buffer layer over a substrate. An active layer is formed on the buffer layer. A top electrode is formed on the active layer. An etch process is performed on the buffer layer and the substrate to define a plurality of pillar structures. The plurality of pillar structures include a first pillar structure laterally offset from a second pillar structure. At least portions of the first and second pillar structures are spaced laterally between sidewalls of the top electrode.

This invention discloses a new switching device supported on a semiconductor that includes a drain disposed on a first surface and a source region disposed near a second surface of said semiconductor opposite the first surface. The switching device further includes an insulated gate electrode disposed on top of the second surface for controlling a source to drain current. The switching device further includes a source electrode interposed into the insulated gate electrode for substantially preventing a coupling of an electrical field between the gate electrode and an epitaxial region underneath the insulated gate electrode. The source electrode further covers and extends over the insulated gate for covering an area on the second surface of the semiconductor to contact the source region. The semiconductor substrate further includes an epitaxial layer disposed above and having a different dopant concentration than the drain region. The insulated gate electrode further includes an insulation layer for insulating the gate electrode from the source electrode wherein the insulation layer having a thickness depending on a Vgsmax rating of the vertical power device.

A vertical field effect transistor includes a first epitaxial region in contact with a top surface of a channel fin extending vertically from a bottom source/drain located above a substrate, a second epitaxial region above the first epitaxial region having a horizontal thickness that is larger than a horizontal thickness of the first epitaxial region. The first epitaxial region and the second epitaxial region form a top source/drain region of the semiconductor structure. The first epitaxial region has a first doping concentration and the second epitaxial region has a second doping concentration that is lower than the first doping concentration. A top spacer, adjacent to the first epitaxial region and the second epitaxial region, is in contact with a top surface of a high-k metal gate stack located around the channel fin and in contact with a top surface of a first dielectric layer disposed between adjacent channel fins.

According to various embodiments, a method for processing an electronic component including at least one electrically conductive contact region may include: forming a contact pad including a self-segregating composition over the at least one electrically conductive contact region to electrically contact the electronic component; forming a segregation suppression structure between the contact pad and the electronic component, wherein the segregation suppression structure includes more nucleation inducing topography features than the at least one electrically conductive contact region for perturbing a chemical segregation of the self-segregating composition by crystallographic interfaces of the contact pad defined by the nucleation inducing topography features.