A uniform moon-shaped bottom spacer for a VTFET device is provided utilizing a replacement bottom spacer that is epitaxially grown above a bottom source/drain region. After filling a trench that is formed into a substrate with a dielectric fill material that also covers the replacement bottom spacer, the replacement bottom spacer is accessed, removed and then replaced with a moon-shaped bottom spacer.

A semiconductor device includes an SiC semiconductor layer which has a first main surface on one side and a second main surface on the other side, a semiconductor element which is formed in the first main surface, a raised portion group which includes a plurality of raised portions formed at intervals from each other at the second main surface and has a first portion in which some of the raised portions among the plurality of raised portions overlap each other in a first direction view as viewed in a first direction which is one of the plane directions of the second main surface, and an electrode which is formed on the second main surface and connected to the raised portion group.

A semiconductor device of embodiments includes: a first silicon carbide region of first conductive type including a first region in contact with a first face of a silicon carbide layer having first and second faces; a second silicon carbide region of second conductive type above the first silicon carbide region; a third silicon carbide region of second conductive type above the second silicon carbide region; a fourth silicon carbide region of first conductive type above the second silicon carbide region; a first gate electrode and a second gate electrode extending in the first direction; a first electrode on the first face and including a first portion and a second portion between the first and the second gate electrode. The first portion contacts the third and the fourth silicon carbide region. The second portion provided in the first direction of the first portion and contacts with the first region.

In some aspects of the present disclosure, a memory device includes a first memory array including: a plurality of memory strings spaced from each other along a first lateral direction and a second lateral direction, each of the plurality of memory strings including a plurality of memory cells arranged along a vertical direction; and a plurality of first conductive structures extending along the vertical direction; wherein each of the plurality of first conductive structures includes a first portion and a second portion; wherein the first portion extends across the plurality of memory cells of a corresponding pair of the plurality of memory strings along the vertical direction, and the second portion is disposed over the first portion along the vertical direction; and wherein the second portion extends farther than the first portion along at least one of the first or second lateral direction.

A semiconductor device includes: a first electrode; a first semiconductor layer; a first insulating film extending downward from an upper surface of the first semiconductor layer, the first insulating film being columnar; a second electrode located in the first insulating film, the second electrode extending in a vertical direction, the second electrode being columnar; a second semiconductor layer partially provided in an upper layer portion of the first semiconductor layer, the second semiconductor layer being next to the first insulating film with the first semiconductor layer interposed; a third semiconductor layer partially provided in an upper layer portion of the second semiconductor layer; and a third electrode located higher than the upper surface of the first semiconductor layer, the third electrode overlapping a portion of the first insulating film, a portion of the first semiconductor layer, and a portion of the second semiconductor layer when viewed from above.

A semiconductor structure and a forming method thereof are provided. The method for forming a semiconductor structure includes providing a base including a semiconductor substrate and a well region located on a surface of the semiconductor substrate, in which the well region includes a plurality of active pillar columns arranged at intervals along a first direction, and each of the active pillar columns includes a plurality of active pillars arranged at intervals along a second direction, in which the first direction is perpendicular to the second direction; forming a plurality of bit line trenches by etching at least the well region and a partial thickness of the semiconductor substrate at bottoms of the active pillars; and forming buried bit lines in the bit line trenches.

A semiconductor device includes first and second vertical transport field-effect transistor (VTFET) devices. Each of the first and second VTFET devices includes a bottom epitaxial layer, a plurality of channel fins formed on the bottom epitaxial layer, a first interlayer dielectric (ILD) layer formed between the channel fins, a high-κ metal gate formed between the channel fins and the first ILD layer, a top epitaxial layer formed discretely on each of the channel fins, and a trench epitaxial layer formed continuously across the top epitaxial layer, a portion of the first ILD layer also being formed between the first and second VTFET device. The semiconductor device also includes a second ILD layer formed on the portion of the first ILD layer that is between the first and second VTFET devices, the second ILD layer separating the top epitaxial layers of the first and second VTFET devices.

A memory device includes a plurality of first memory cells disposed along a vertical direction. Each of the plurality of first memory cells includes a portion of a first channel segment that extends along the vertical direction and has a first sidewall and a second sidewall. The first and second sidewalls of the first channel segment facing toward and away from a first lateral direction, respectively. Each of the plurality of first memory cells includes a portion of a first ferroelectric segment that also extends along the vertical direction and is in contact with the first sidewall of the first channel segment. A width of the first ferroelectric segment along a second lateral direction is different from a width of the first channel segment along the second lateral direction. The second lateral direction is perpendicular to the first lateral direction.

A method of soldering elements together includes providing a substrate having a metal die attach surface, providing a semiconductor die that is configured as a power semiconductor device and having a semiconductor body, a rear side metallization, and a front side layer stack, the front side layer stack having a front side metallization and a contaminant protection layer, arranging the semiconductor die on the substrate with a region of solder material between the die attach surface and the rear side metallization, and performing a soldering process that reflows the region of solder material to form a soldered joint between the metal die attach surface and the rear side metallization, wherein the soldering process comprises applying mechanical pressure to the front side metallization.

According to an aspect of the disclosure, a semiconductor device is provided. The semiconductor device includes a stack of insulating layers and interconnect layers that are positioned alternatingly over a substrate. The semiconductor device includes a channel structure extending from the substrate and further through the insulating layers and the interconnect layers. The channel structure includes a first channel section positioned over the substrate and coupled to a first group of the interconnect layers, and a second channel section positioned over the first channel section and coupled to a second group of the interconnect layers. The semiconductor device also includes a plurality of contact structures extending from and coupled to the interconnect layers in a staircase configuration such that each of the plurality of contact structures extends from a respective interconnect layer.