Implementations of semiconductor devices may include: an isolated drain finger, a gate ring, and a source ring; wherein the gate ring surrounds a perimeter of the isolated drain finger; wherein the source ring surrounds an outer perimeter of the gate ring and the isolated drain finger; wherein a gate bus is coupled to the gate ring; wherein a first electrically insulative portion is located between the isolated drain finger and the gate ring; and wherein a second electrically insulative portion is located between the gate and the source ring.

A semiconductor device is configured including a p-type back barrier layer provided over a substrate and formed from a p-type nitride semiconductor in which Mg or Zn is doped, a nitride semiconductor stacked structure provided over the p-type back barrier layer, the nitride semiconductor stacked structure including an electron transit layer and an electron supply layer, a source electrode, a drain electrode and a gate electrode provided over the nitride semiconductor stacked structure, and a groove extending to the p-type back barrier layer.

Circuit-Under-Pad (CUP) device topologies for high-current lateral power switching devices are disclosed, in which the interconnect structure and pad placement are configured for reduced source and common source inductance. In an example topology for a power semiconductor device comprising a lateral GaN HEMT, the source bus runs across a centre of the active area, substantially centered between first and second extremities of source finger electrodes, with laterally extending tabs contacting the underlying source finger electrodes. The drain bus is spaced from the source bus and comprises laterally extending tabs contacting the underlying drain finger electrodes. The gate bus is centrally placed and runs adjacent the source bus. Preferably, the interconnect structure comprises a dedicated gate return bus to separate the gate drive loop from the power loop. Proposed CUP device structures provide for lower source and common source inductance and/or higher current carrying capability per unit device area.

According to one embodiment, a semiconductor device includes first to third electrodes, first and second semiconductor regions, and a first member. The first semiconductor region includes Al.sub.x1Ga.sub.1-x1N (0≤x1<1). The second semiconductor region includes Al.sub.x2Ga.sub.1-x2N (x1<x2≤1). The first member includes first and second regions. The second region is between the first region and the first electrode region of the second electrode. A part of the second region is between the second semiconductor portion of the second semiconductor region and the second electrode region. The second region includes at least one first element selected from the group consisting of Ti, Al, Ga, Ni, Nb, Mo, Ta, Hf, V, and Au. The first region does not include the first element, or a concentration of the first element in the first region is lower than a concentration of the first element in the second region.

A field-effect transistor includes: a nitride semiconductor layer that includes a heterojunction; a source electrode and a drain electrode; a first gate electrode that is disposed to surround the drain electrode in a plan view and performs a normally-on operation; and a second gate electrode is disposed to surround the first gate electrode in a plan view and performs a normally-off operation. The first gate electrode and the second gate electrode include straight portions in which both an edge of the first gate electrode and an edge of the second gate electrode are substantially straight in the plan view and end portions formed by corner portions which are curved or bent in the plan view. An interval, a length, or a radius of curvature of one of the first gate electrode, the second gate electrode, and the source electrode is set such that concentration of an electric field at the end portion is alleviated.

A magnetic-field-sensitive MOSFET (MagFET) is described herein. In accordance with one embodiment, the MagFET comprises a semiconductor body, a first well region arranged in the semiconductor body and being doped with dopants of a first doping type, and a number of N contact regions arranged in the first well region and doped with dopants of a second doping type, which is complementary to the first doping type, wherein N is equal to or greater than three. A gate electrode covers the first well region between the contact regions. The gate electrode is separated from the first well region by an isolation layer and is configured to control a charge carrier density in the first well region between the contact regions dependent on a voltage applied at the gate electrode. The first well region has a center of symmetry and the contact regions are arranged rotationally symmetric with respect to the center of symmetry with a rotational symmetry of order N.

A vertical field effect transistor is provided as follows. A substrate has a lower drain and a lower source arranged along a first direction in parallel to an upper surface of the substrate. A fin structure is disposed on the substrate and extended vertically from the upper surface of the substrate. The fin structure includes a first end portion and a second end portion arranged along the first direction. A bottom surface of a first end portion of the fin structure and a bottom surface of a second end portion of the fin structure overlap the lower drain and the lower source, respectively. The fin structure includes a sidewall having a lower sidewall region, a center sidewall region and an upper sidewall region. A gate electrode surrounds the center side sidewall region of the fin structure.

RF transistor amplifiers are provided that include a submount and an RF transistor amplifier die that is mounted on top of the submount. A multi-layer encapsulation is formed that at least partially covers the RF transistor amplifier die. The multi-layer encapsulation includes a first dielectric layer and a first conductive layer, where the first dielectric layer is between a top surface of the RF transistor amplifier die and the first conductive layer.

A nitride semiconductor device includes an electron transit layer (103) that is formed of a nitride semiconductor, an electron supply layer (104) that is formed on the electron transit layer (103), that is formed of a nitride semiconductor whose composition is different from the electron transit layer (103) and that has a recess (109) which reaches the electron transit layer (103) from a surface, a thermal oxide film (111) that is formed on the surface of the electron transit layer (103) exposed within the recess (109), a gate insulating film (110) that is embedded within the recess (109) so as to be in contact with the thermal oxide film (111), a gate electrode (108) that is formed on the gate insulating film (110) and that is opposite to the electron transit layer (103) across the thermal oxide film (111) and the gate insulating film (110), and a source electrode (106) and a drain electrode (107) that are provided on the electron supply layer (104) at an interval such that the gate electrode (108) intervenes therebetween.

A semiconductor unit includes: a barrier layer including a first compound semiconductor; a channel layer including a second compound semiconductor, and bonded to the barrier layer at a first face; an insulation layer provided on a second face, of the barrier layer, that is on an opposite side of the first face, and having an opening section that exposes the barrier layer; a gate electrode provided to bury the opening section; a source electrode and a drain electrode that are provided on the second face of the barrier layer on both sides of the gate electrode with the gate electrode being interposed; and a material layer including a metal material or a semiconductor material, and provided in contact with the second face of the barrier layer between the gate electrode and the drain electrode.