A device having a channel with multiple voltage thresholds is provided. The channel can include a first section located adjacent to a source electrode, which is a normally-off channel and a second section located between the first section and a drain electrode, which is a normally-on channel. The device can include a charge-controlling electrode connected to the source electrode, which extends from the source electrode over at least a portion of the second section of the channel. During operation of the device, a potential difference between the charge-controlling electrode and the channel can control the on/off state of the normally-on section of the channel.

Embodiments of a silicon carbide (SiC) device are provided herein. In some embodiments, a silicon carbide (SiC) device may include a gate electrode disposed above a SiC semiconductor layer, wherein the SiC semiconductor layer comprises: a drift region having a first conductivity type; a well region disposed adjacent to the drift region, wherein the well region has a second conductivity type; and a source region having the first conductivity type disposed adjacent to the well region, wherein the source region comprises a source contact region and a pinch region, wherein the pinch region is disposed only partially below the gate electrode, wherein a sheet doping density in the pinch region is less than 2.5×10.sup.14 cm.sup.−2, and wherein the pinch region is configured to deplete at a current density greater than a nominal current density of the SiC device to increase the resistance of the source region.

An integrated circuit containing a first plurality of MOS transistors operating in a low voltage range, and a second plurality of MOS transistors operating in a mid voltage range, may also include a high-voltage MOS transistor which operates in a third voltage range significantly higher than the low and mid voltage ranges, for example 20 to 30 volts. The high-voltage MOS transistor has a closed loop configuration, in which a drain region is surrounded by a gate, which is in turn surrounded by a source region, so that the gate does not overlap field oxide. The integrated circuit may include an n-channel version of the high-voltage MOS transistor and/or a p-channel version of the high-voltage MOS transistor. Implanted regions of the n-channel version and the p-channel version are formed concurrently with implanted regions in the first and second pluralities of MOS transistors.

Devices and methods related to radio-frequency (RF) switches having reduced-resistance metal layout. In some embodiments, a field-effect transistor (FET) based RF switch device can include a plurality of fingers arranged in an interleaved configuration such that a first group of the fingers are electrically connected to a source contact and a second group of the fingers are electrically connected to a drain contact. At least some of the fingers can have a current carrying capacity that varies as a function of location along a direction in which the fingers extend. Such a configuration of the fingers can desirably reduce the on-resistance (Ron) of the FET based RF switch device.

The present disclosure attempts to provide a capacitor cell having a large capacitance value per unit area in a semiconductor integrated circuit device using a three-dimensional transistor device. A logic cell includes a three-dimensional transistor device. A capacitor cell includes a three-dimensional transistor device. A length of a portion, of a local interconnect, which protrudes from a three-dimensional diffusion layer in a direction away from a power supply interconnect in the capacitor cell is greater than a length of a portion, of a local interconnect, which protrudes from a three-dimensional diffusion layer in a direction away from a power supply interconnect in the logic cell.

We disclose a III-nitride semiconductor based heterojunction power device comprising: a first heterojunction transistor formed on a substrate (4) and a second heterojunction transistor formed on the substrate. The first heterojunction transistor comprises: first III-nitride semiconductor region formed over the substrate, wherein the first III-nitride semiconductor region comprises a first heterojunction comprising at least one two dimensional carrier gas; a first terminal (8) operatively connected to the first III-nitride semiconductor region; a second terminal (9) laterally spaced from the first terminal and operatively connected to the first III-nitride semiconductor region; and a first gate region (10) over the first III-nitride semiconductor region between the first and second terminals. The second heterojunction transistor comprises: a second III-nitride semiconductor region formed over the substrate, wherein the second III-nitride semiconductor region comprises a second heterojunction comprising at least one two dimensional carrier gas; a third terminal (19) operatively connected to the second III-nitride semiconductor region; a fourth terminal (16) laterally spaced from the third terminal in the first dimension and operatively connected to the second III-nitride semiconductor region; a first plurality of highly doped semiconductor regions (18) of a first conductivity type formed over the second III-nitride semiconductor region, the first plurality of highly doped semiconductor regions being formed between the third terminal and the fourth terminal; and a second gate region (17) operatively connected to the first plurality of highly doped semiconductor regions. One of the first and second heterojunction transistors is an enhancement mode field effect transistor and the other of the first and second heterojunction transistors is a depletion mode field effect transistor.

A bidirectional switch module includes a plurality of bidirectional switches and a mount board. Each of the plurality of bidirectional switches includes a first source electrode, a first gate electrode, a second gate electrode, and a second source electrode. On the mount board, the plurality of bidirectional switches are mounted. In the bidirectional switch module, the plurality of bidirectional switches are connected in parallel.

A spatial terahertz wave phase modulator based on the high electron mobility transistor is provided. The phase modulator combines the quick-response high electron mobility transistor with a novel metamaterial resonant structure, so as to rapidly modulate terahertz wave phases in a free space. The phase modulator includes a semiconductor substrate, an HEMT epitaxial layer, a periodical metamaterial resonant structure and a muff-coupling circuit. A concentration of 2-dimensional electron gas in the HEMT epitaxial layer is controlled through loading voltage signals, so as to change an electromagnetic resonation mode of the metamaterial resonant structure, thereby achieving phase modulation of terahertz waves. The phase modulator has a phase modulation depth of over 90 degrees within a large bandwidth, and a maximum phase modulation depth is about 140 degrees. Furthermore, the phase modulator is simple in structure, easy to machine, high in modulation speed, convenient to use, and easy to package.

A diode and method of design the layout of the same having reduced parasitic capacitance is disclosed. In particular, the diode for providing fast response protection of an RF circuit from a high power noise event, such as an ESD, voltage spike, power surge or other noise is disclose. The parasitic capacitance in disclosed circuit is a greatly reduced compared to the prior art, thus significantly increasing the speed of the response to dissipate all high power noise events.

According to one configuration, a fabricator produces an electronic device to include: a substrate; a transistor circuit disposed on the substrate; silicide material disposed on first regions of the transistor circuit; and the silicide material absent from second regions of the transistor circuit. Absence of the silicide material over the second regions of the respective of the transistor circuit increases a resistance of one or more parasitic paths (such as one or more parasitic transistors) in the transistor circuit. The increased resistance in the one or more parasitic paths provides better protection of the transistor circuit against electro-static discharge conditions.