Methods and devices that include a multigate device having a channel layer disposed between a source feature and a drain feature, a metal gate that surrounds the channel layer, and a first air gap spacer interposing the metal gate and the source feature and a second air gap spacer interposing the metal gate and the drain feature. A backside contact extends to the source feature. A power line metallization layer is connected to the backside contact.

A semiconductor device includes a semiconductor substrate, a first current-carrying electrode, a second current-carrying electrode, a first control electrode disposed between the first current-carrying electrode and the second current-carrying electrode, a third current-carrying electrode electrically coupled to the first current-carrying electrode, and a fourth current-carrying electrode adjacent the third current-carrying electrode. The third current-carrying electrode and the fourth current-carrying electrode are configured to support current flow from the third current-carrying electrode to the fourth current-carrying electrode parallel to a second direction. The fourth current-carrying element is electrically coupled to the second current-carrying electrode and a second control electrode. The second control electrode is electrically coupled to the first control electrode. A first crossing region is electrically coupled to the first control electrode and a second crossing region is electrically coupled to the fourth current-carrying electrode, wherein the second crossing region crosses a portion of the first crossing region.

A transistor includes a semiconductor substrate having first and second terminals. An interconnect structure, on an upper surface of the substrate, is formed of layers of dielectric material and electrically conductive material. The conductive material includes a first pillar connected with the first terminal, a second pillar connected with the second terminal, and a shield system between the first and second pillars. The shield system includes forked structures formed in at least two conductive layers of the interconnect structure and at least partially surrounding segments of the second pillar. The shield system may additionally include shield traces formed in a first conductive layer positioned between gate fingers and the first pillars and/or the shield system may include shield runners that are located in an electrically conductive layer that is below a topmost electrically conductive layer with the first pillar being connected to a runner in the topmost conductive layer.

A transistor amplifier package includes a base, one or more transistor dies on the base, first and second leads coupled to the one or more transistor dies and defining respective radio frequency (RF) signal paths, and an isolation structure on the base between the respective RF signal paths. The isolation structure includes first and second wire bonds. The first and second wire bonds may have a crossed configuration defining at least one cross point therebetween. Related wire bond-based isolation structures are also discussed.

Semiconductor devices, such as a lateral HEMT, may display current flow between a plurality of interdigitated source fingers and drain fingers, and controlled by a common gate connection. An extended source finger contact may enable improved voltage control across the source fingers, even for large devices with many and/or lengthy source fingers. In this way, unwanted subthreshold operations and switching oscillations may be avoided by reliably maintaining a source voltage at a desired level, to thereby provide fast and reliable switching.

A semiconductor device includes a first semiconductor layer formed of a nitride semiconductor on a substrate, a second semiconductor layer formed of a nitride semiconductor on the first semiconductor layer, a gate trench formed in the second semiconductor layer or in the second and first semiconductor layers, a gate electrode formed at the gate trench, and a source electrode and a drain electrode formed on the second semiconductor layer. The gate trench has terminal parts of a bottom of the gate trench formed shallower than a center part of the bottom. A part of a sidewall of the gate trench is formed of a surface including an a-plane. The center part of the bottom is a c-plane. The terminal parts of the bottom form a slope from the c-plane to the a-plane.

A semiconductor device has a first wiring extending in a first direction on a nitride semiconductor layer. A source electrode is electrically connected to the first wiring and extends in a second direction. A drain electrode extends in the second direction and includes a first and second portion extending in the second direction, spaced from each other in the first direction. An element isolation region is in the second nitride semiconductor layer between the first and second portions. A third portion extends in the second direction on the first and second portions. A gate electrode extends in the second direction on the second nitride semiconductor layer between the source electrode and the drain electrode. The portion includes holes therein aligned with each other along the second direction with the spacing between adjacent holes in the second direction increasing with increasing distance in the second direction from the first wiring.

A HEMT structure includes a compound semiconductor substrate, a gate electrode, a source electrode, a drain electrode, a first metal pillar, a second metal pillar, a dielectric layer, and a metal layer. The gate electrode is disposed on the compound semiconductor substrate. The source electrode is disposed on the compound semiconductor substrate at a first side of the gate electrode. The drain electrode is disposed on the compound semiconductor substrate at a second side of the gate electrode. The first metal pillar is disposed on the source electrode. The second metal pillar is disposed on the drain electrode. The dielectric layer is disposed on the compound semiconductor substrate. The dielectric layer surrounds the gate electrode, the first metal pillar, and the second metal pillar. The metal layer is disposed on the dielectric layer. The metal layer straddles the gate electrode, the first metal pillar, and the second metal pillar.

There is provided a semiconductor device including a multi-gate transistor having a plurality of gates in a common active region, in which the multi-gate transistor has a comb-shaped metal structure in which a first metal is drawn out and bundled in a W length direction from contacts arranged in a single row in each of a source region and a drain region, and the multi-gate transistor has a wiring layout in which a root section of the first metal coincides immediately above an end of the source region and the drain region or is disposed inside the end of the source region and the drain region in the W length direction.

An amplifier has a plurality of gate finger electrodes, two gate connection electrodes, a plurality of source electrodes and a plurality of drain electrodes, and a plurality of drain connection elements. The plurality of gate finger electrodes are arranged pectinate on the surface of the active region of the semiconductor substrate. The two gate connection electrodes connect in common each of both ends of the plurality of gate finger electrodes. The plurality of source electrodes and the plurality of drain electrodes are arranged alternately on the surface of the semiconductor substrate between the plurality of gate finger electrodes. The plurality of drain connection elements connects in sequence the plurality of drain electrodes. The ratio of the inductance value of each drain connection element to the parasitic capacitance of the drain-source electrodes between the corresponding drain electrode and the source electrode is constant.