A transistor includes a plurality of gate fingers that extend in a first direction and are spaced apart from each other in a second direction, each of the gate fingers comprising at least spaced-apart and generally collinear first and second gate finger segments that are electrically connected to each other. The first gate finger segments are separated from the second gate finger segments in the first direction by a gap region that extends in the second direction. A resistor is disposed in the gap region.

A semiconductor device includes a substrate having a front surface including a first long side and a second long side extending in a first direction and opposed to each other, and a first short side and a second short side extending in a second direction intersecting the first direction and opposed to each other, a source finger provided on the front surface, a drain finger provided on the front surface, and a gate finger provided on the front surface and sandwiched between the source finger and the drain finger, wherein a via hole penetrating the substrate is provided in the substrate, a region where the via hole is connected to the source finger in the front surface is contained within the source finger, and the via hole has a maximum width in the first direction larger than a maximum width in the second direction.

GaN-based half bridge power conversion circuits employ control, support and logic functions that are monolithically integrated on the same devices as the power transistors. In some embodiments a low side GaN device communicates through one or more level shift circuits with a high side GaN device. Various embodiments of level shift circuits and their inventive aspects are disclosed.

Provided is a compound semiconductor device that can suppress the deterioration of the element characteristics and a method of manufacturing a compound semiconductor device. The compound semiconductor device includes a laminated body constituted of a compound semiconductor and including a channel layer in which a first conductivity type carrier runs; a gate electrode provided on an upper surface side of the laminated body; a source electrode provided on the upper surface side of the laminated body; and a drain electrode provided on the upper surface side of the laminated body. The laminated body includes a second conductivity type first low resistance layer that is provided at a position facing the gate electrode and is in contact with the gate electrode, a first electric-field relaxation layer extended from the first low resistance layer toward a side of one of the source electrode and the drain electrode and configured to relax electric field concentration to the first low resistance layer, and a first amorphous layer covering a first side surface that is a side surface of the first electric-field relaxation layer and faces one of the source electrode and the drain electrode.

A power amplifier comprising a GaN-based high electron mobility transistor (HEMT) device, wherein a power added efficiency (PAE) of the power amplifier is greater than 32% at P1DB during operation of the power amplifier between 26.5 GHz and 30.5 GHz.

Electron gas transistor of normally open type, includes a first semiconductor layer laid out along a layer plane and a second semiconductor layer formed on the first semiconductor layer and laid out along the layer plane, the first and second semiconductor layers forming an electron gas layer at the interface thereof; a third semiconductor layer with P type doping formed on the second semiconductor layer and laid out along the layer plane, a first zone with N type doping of which a part is arranged within the thickness of the third semiconductor layer, the first zone-delimiting a source zone; a second zone with N or metal type doping having at least one part arranged in the second semiconductor layer; a source electrode formed on the source zone; a drain electrode formed on the first semiconductor layer; and a gate located between the source electrode and the second zone.

A gallium nitride (GaN) device, where a drain of the GaN device includes a p-type (P-GaN) layer and a drain metal. The drain metal includes a plurality of first structural intervals and a plurality of second structural intervals. The plurality of first structural intervals and the plurality of second structural intervals are alternately distributed in the gate width direction. In this way, the drain metal implements local injection of holes for the device in the first structural intervals, and forms ohmic contact in the second structural intervals, implementing current conduction from a drain to a source of the device.

An integrated circuit includes an extended drain MOS transistor with parallel alternating active gap drift regions and field gap drift regions. The extended drain MOS transistor includes a gate having field plates over the field gap drift regions. The extended drain MOS transistor may be formed in a symmetric nested configuration. A process for forming an integrated circuit containing an extended drain MOS transistor provides parallel alternating active gap drift regions and field gap drift regions with a gate having field plates over the field gap drift regions.

A semiconductor device includes a substrate having an upper surface including a recess region, a semiconductor structure on the substrate, a portion of the semiconductor structure within the recess region, and a gate contact, a drain contact, and a source contact on the semiconductor structure. The recess region does not vertically overlap the drain contact or the source contact.

A semiconductor device structure for a power transistor structure wherein a drain terminal structure comprises field plates to control and reduce the peak intensity of the channel electric field at the drain terminal. By forming multiple field plates with the existing metallization layers, the generation of hot carriers and impact ionization near the drain can be reduced. For example, in a GaN HEMT, this effect is achieved with two field plates that have different capacitive coupling and overlap with the drain ohmic contact to achieve a reduction in the channel electric field. The use of this drain terminal structure may offer a reduction in increase of R.sub.dson with aging that may be observed in devices after high voltage stress.