A semiconductor device and a method of forming the same are provided. A semiconductor device according to the present disclosure includes a first source/drain feature, a second source/drain feature, a first semiconductor channel member and a second semiconductor channel member extending between the first and second source/drain features, and a first dielectric feature and a second dielectric feature each including a first dielectric layer and a second dielectric layer different from the first dielectric layer. The first and second dielectric features are sandwiched between the first and second semiconductor channel members.

Techniques described herein enable respective (different) types of metal silicide layers to be formed for p-type source/drain regions and n-type source/drain regions in a selective manner. For example, a p-type metal silicide layer may be selectively formed over a p-type source/drain region (e.g., such that the p-type metal silicide layer is not formed over the n-type source/drain region) and an n-type metal silicide layer may be formed over the n-type source/drain region (which may be selective or non-selective). This provides a low Schottky barrier height between the p-type metal silicide layer and the p-type source/drain region, as well as a low Schottky barrier height between the n-type metal silicide layer and the n-type source/drain region. This reduces the contact resistance for both p-type source/drain regions and n-type source/drain regions.

A display panel and a mobile terminal are provided. The display panel includes a base and a thin film transistor (TFT) layer that is disposed on the base and includes at least two TFTs arranged in parallel. According to the present disclosure, the TFT layer includes at least two TFTs arranged in parallel, thereby resolving the problem that a short circuit between a gate and a source and/or a short circuit between the gate and a drain in the TFT cannot be repaired.

A method includes depositing a high-k gate dielectric layer over and along sidewalls of a semiconductor fin. The method further includes depositing an n-type work function metal layer over the high-k gate dielectric layer and performing a passivation treatment on the high-k gate dielectric layer through the n-type work function metal layer. The passivation treatment comprises a remote plasma process. The method further includes depositing a fill metal over the n-type work function metal layer to form a metal gate stack over the high-k gate dielectric layer. The metal gate stack comprising the n-type work function metal layer and the fill metal.

A method includes providing a semiconductor structure having a metal gate structure (MG), gate spacers disposed on sidewalls of the MG, and a source/drain (S/D) feature disposed adjacent to the gate spacers; forming a first metal layer over the S/D feature and between the gate spacers; recessing the first metal layer to form a trench; forming a dielectric layer on sidewalls of the trench; forming a second metal layer over the first metal layer in the trench, wherein sidewalls of the second metal layer are defined by the dielectric layer; and forming a contact feature over the MG to contact the MG.

A device includes a fin extending from a substrate; a gate stack over and along sidewalls of the fin; a gate spacer along a sidewall of the gate stack; an epitaxial source/drain region in the fin and adjacent the gate spacer, the epitaxial source/drain region including a first epitaxial layer on the fin, the first epitaxial layer including silicon and arsenic; and a second epitaxial layer on the first epitaxial layer, the second epitaxial layer including silicon and phosphorus, the first epitaxial layer separating the second epitaxial layer from the fin; and a contact plug on the second epitaxial layer.

A vertical FET includes a channel fin between a bottom source/drain (S/D) region and a top S/D region, a gate upon a sidewall of the channel fin, a top metallization upon the top S/D region, a first contact metallization connected to the gate, a second contact metallization connected to the bottom S/D region, a first vertical liner between a portion of the gate and the first contact metallization, and a second vertical liner between the top metallization and the second contact metallization. The vertical FET may be fabricated by forming a self-aligned block and utilizing the self-aligned block to e.g., prevent gate to gate shorting during replacement gate formation or processing.

Backside interconnect structures having reduced critical dimensions for semiconductor devices and methods of forming the same are disclosed. In an embodiment, a device includes a first transistor structure over a front-side of a substrate; a first backside interconnect structure over a backside of the substrate, the first backside interconnect structure including first conductive features having tapered sidewalls with widths that narrow in a direction away from the substrate; a power rail extending through the substrate, the power rail being electrically coupled to the first conductive features; and a first source/drain contact extending from the power rail to a first source/drain region of the first transistor structure.

In an embodiment, a structure includes: a contact etch stop layer (CESL) over a substrate; a fin extending through the CESL; an epitaxial source/drain region in the fin, the epitaxial source/drain region extending through the CESL; a silicide contacting upper facets of the epitaxial source/drain region; a source/drain contact contacting the silicide, lower facets of the epitaxial source/drain region, and a first surface of the CESL; and an inter-layer dielectric (ILD) layer surrounding the source/drain contact, the ILD layer contacting the first surface of the CESL.

The present disclosure is directed to gate-all-around (GAA) transistor structures with a low level of leakage current and low power consumption. For example, the GAA transistor includes a semiconductor layer with a first source/drain (S/D) epitaxial structure and a second S/D epitaxial structure disposed thereon, where the first and second S/D epitaxial structures are spaced apart by semiconductor nano-sheet layers. The semiconductor structure further includes isolation structures interposed between the semiconductor layer and each of the first and second S/D epitaxial structures. The GAA transistor further includes a gate stack surrounding the semiconductor nano-sheet layers.