Semiconductor devices and their manufacturing methods are disclosed herein, and more particularly to semiconductor devices including a transistor having gate all around (GAA) transistor structures and manufacturing methods thereof. The methods described herein allow for complex shapes (e.g., “L-shaped”) to be etched into a multi-layered stack to form fins used in the formation of active regions of the GAA nanostructure transistor structures. In some embodiments, the active regions may be formed with a first channel width and a first source/drain region having a first width and a second channel width and a second source/drain region having a second width that is less than the first width.

Semiconductor devices and methods are provided. A semiconductor device according to the present disclosure includes a first transistor in a first area and a second transistor in a second area. The first transistor includes a first gate structure extending lengthwise along a first direction, and a first gate spacer, a second gate spacer, and a third gate spacer over sidewalls of the first gate structure. The second transistor includes a second gate structure extending lengthwise along the first direction, and the first gate spacer and the third gate spacer over sidewalls of the second gate structure. The first gate spacer, the second gate spacer and the third gate spacer are of different compositions and the third gate spacer is directly on the first gate spacer in the second area.

A semiconductor device includes first transistor having a first gate stack and first source/drain regions on opposing sides of the first gate stack; a second transistor having a second gate stack and second source/drain regions on opposing sides of the second gate stack; and a gate isolation structure separating the first gate stack from the second gate stack. The gate isolation structure includes a dielectric liner having a varied thickness along sidewalls of the first gate stack and the second gate stack and a dielectric fill material over the dielectric liner, wherein the dielectric fill material comprises a seam.

According to the present disclosure, hybrid fins positioned between two different epitaxial source/drain features are recessed to prevent conductive material from entering interior air gaps of the hybrid fins, thus, preventing short circuit between source/drain contacts and gate electrodes. Recessing the hybrid fins may be achieved by enlarging mask during semiconductor fin etch back, therefore, without increasing production cost.

A titanium precursor is used to selectively form a titanium silicide (TiSi.sub.x) layer in a semiconductor device. A plasma-based deposition operation is performed in which the titanium precursor is provided into an opening, and a reactant gas and a plasma are used to cause silicon to diffuse to a top surface of a transistor structure. The diffusion of silicon results in the formation of a silicon-rich surface of the transistor structure, which increases the selectivity of the titanium silicide formation relative to other materials of the semiconductor device. The titanium precursor reacts with the silicon-rich surface to form the titanium silicide layer. The selective titanium silicide layer formation results in the formation of a titanium silicon nitride (TiSi.sub.xN.sub.y) on the sidewalls in the opening, which enables a conductive structure such as a metal source/drain contact to be formed in the opening without the addition of another barrier layer.

A method of manufacturing a semiconductor device includes forming a fin structure in which first semiconductor layers and second semiconductor layers are alternatively stacked, the first and second semiconductor layers having different material compositions; forming a sacrificial gate structure over the fin structure; forming a gate spacer on sidewalls of the sacrificial gate structure; etching a source/drain (S/D) region of the fin structure, which is not covered by the sacrificial gate structure and the gate spacer, thereby forming an S/D trench; laterally etching the first semiconductor layers through the S/D trench, thereby forming recesses; selectively depositing an insulating layer on surfaces of the first and second semiconductor layers exposed in the recesses and the S/D trench, but not on sidewalls of the gate spacer; and growing an S/D epitaxial feature in the S/D trench, thereby trapping air gaps in the recesses.

The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, first and second contact structures proximate to each other and over the substrate, and first and second dielectric layers formed over the first and second contact structures, respectively. A top portion of the first dielectric layer can include a first dielectric material. A bottom portion of the first dielectric layer can include a second dielectric material different from the first dielectric material. The second dielectric layer can include a third dielectric material different from the first dielectric material.

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a fin, a gate structure positioned on the fin, impurity regions positioned on two sides of the fin, contacts positioned on the impurity regions, and conductive covering layers positioned on the contacts. The conductive covering layers are formed of copper germanide.

Semiconductor devices and methods of forming the same are provided. In one embodiment, a semiconductor device includes a fin extending from a substrate, a gate structure over a channel region of the fin, a source/drain contact over a source/drain region of the fin, a spacer extending along a sidewall of the gate structure, a liner extending along a sidewall of the source/drain contact, a gate contact via over and electrically coupled to the gate structure, and a source/drain contact via over and electrically coupled to the source/drain contact. The gate contact via extends through a first dielectric layer such that a portion of the first dielectric layer interposes between the gate contact via and the spacer. The source/drain contact via extends through a second dielectric layer such that a portion of the second dielectric layer interposes between the source/drain contact via and the liner.

An exemplary device includes a channel layer, a first epitaxial source/drain feature, and a second epitaxial source/drain feature disposed over a substrate. The channel layer is disposed between the first epitaxial source/drain feature and the second epitaxial source/drain feature. A metal gate is disposed between the first epitaxial source/drain feature and the second epitaxial source/drain feature. The metal gate is disposed over and physically contacts at least two sides of the channel layer. A source/drain contact is disposed over the first epitaxial source/drain feature. A doped crystalline semiconductor layer, such as a gallium-doped crystalline germanium layer, is disposed between the first epitaxial source/drain feature and the source/drain contact. The doped crystalline semiconductor layer is disposed over and physically contacts at least two sides of the first epitaxial source/drain feature. In some embodiments, the doped crystalline semiconductor layer has a contact resistivity that is less than about 1×10.sup.−9 Ω-cm.sup.2.