Provided are methods of manufacturing comprising providing a FET base structure, the FET base structure comprising a substrate, a drain and a source; and providing a channel layer on the FET base structure; and providing a first layer on the FET base structure. The first layer comprises a one-dimensional or two-dimensional material and is arranged on an upper surface of the channel layer so as to form a sensing surface of the FET. The step of providing the channel layer comprises forming the channel layer and subsequently transferring the channel layer onto the FET base structure. Alternatively or additionally, the step of providing the first layer on the FET base structure comprises forming the first layer and subsequently transferring the first layer onto the FET base structure.

A nitride semiconductor device includes: a substrate; a first nitride semiconductor layer of a first conductivity type; a second nitride semiconductor layer of a second conductivity type; an electron transport layer and an electron supply layer provided, in that order from a side on which the substrate is located, above the second nitride semiconductor layer and on an inner surface of a first opening; a gate electrode provided above the electron supply layer and covering the first opening; a source electrode provided in a second opening and connected to the second nitride semiconductor layer; a drain electrode; a third opening at an outermost edge part in a plan view of the substrate; and a potential fixing electrode provided in the third opening, the potential fixing electrode being connected to the second nitride semiconductor layer and in contact with neither the electron transport layer nor the electron supply layer.

The present invention relates to a semiconductor device with an asymmetric gate structure. The device comprises a substrate; a channel layer, positioned above the substrate; a barrier layer, positioned above the channel layer, the barrier layer and the channel layer being configured to form two-dimensional electron gas (2DEG), and the 2DEG being formed in the channel layer along an interface between the channel layer and the barrier layer; a source contact and a drain contact, positioned above the barrier layer; a doped group III-V layer, positioned above the barrier layer and between the drain contact and the source contact; and a gate electrode, positioned above the doped group III-V layer and configured to form a Schottky junction with the doped group III-V layer, wherein the doped group III-V layer and/or gate electrode has a non-central symmetrical geometry so as to achieve the effect of improving gate leakage current characteristics.

The present disclosure provides a semiconductor device and a fabrication method thereof. The semiconductor device includes a III-nitride layer, a gate, a connection structure, and a gate bus. The gate is disposed over the III-nitride layer. The connection structure is disposed over the gate. The gate bus extends substantially in parallel to the gate and disposed over the connection structure from a top view perspective. The gate bus is electrically connected to the gate through the connection structure.

Some embodiments of the disclosure provide a semiconductor device. The semiconductor device comprises: a substrate; a first nitride semiconductor layer on the substrate; a second nitride semiconductor layer on the first nitride semiconductor layer and having a band gap greater than a band gap of the first nitride semiconductor layer; a group III-V dielectric layer disposed on the second nitride semiconductor layer; a gate electrode disposed on the second nitride semiconductor layer; and a first passivation layer disposed on the group III-V dielectric layer, wherein the group III-V dielectric layer is separated from the gate electrode by the first passivation layer.

Some embodiments of the disclosure provide a semiconductor device. The semiconductor device comprises: a substrate; a first nitride semiconductor layer disposed on the substrate; a second nitride semiconductor layer disposed on the first nitride semiconductor layer and having a bandgap greater than that of the first nitride semiconductor layer; an ohmic contact disposed on the first nitride semiconductor layer; and a spacer disposed adjacent to a sidewall of the ohmic contact.

Semiconductor device structures and methods for manufacturing the same are provided. The semiconductor device structure includes a substrate, a first nitride semiconductor layer, a second nitride semiconductor layer, a gate structure, a first spacer, a second spacer and a drain electrode. The first nitride semiconductor layer is disposed on the substrate. The second nitride semiconductor layer is disposed on the first nitride semiconductor layer. The gate structure is disposed on the second nitride semiconductor layer. The first spacer is disposed adjacent to a first surface of the gate structure. The second spacer is disposed adjacent to a second surface of the gate structure. The drain electrode is disposed relatively adjacent to the second spacer than the first space. The first spacer has a first length, and the second spacer has a second length greater than the first length along the first direction.

A semiconductor device includes a drain electrode, a first source electrode, a second source electrode, a first gate electrode, and a second gate electrode. The first gate electrode is arranged between the first source electrode and the drain electrode. The first gate electrode extends along a first direction. The second gate electrode is arranged between the second source electrode and the drain electrode. The second gate electrode extends along the first direction. The first gate electrode is arranged above a first imaginary line substantially perpendicular to the first direction in a top view of the semiconductor device and the second gate electrode is arranged below a second imaginary line substantially perpendicular to the first direction in the top view of the semiconductor device.

A transistor device includes a semiconductor structure, source and drain contacts on the semiconductor structure, a gate on the semiconductor structure between the source and drain contacts, and a surface passivation layer on the semiconductor structure between the gate and the source or drain contact. The surface passivation layer includes an opening therein that exposes a first region of the semiconductor structure for processing the first region differently than a second region of the semiconductor structure adjacent the gate. Related devices and fabrication methods are also discussed.

A method of forming a high electron mobility transistor (HEMT) includes: providing a semiconductor structure comprising a channel layer and a barrier layer sequentially stacked on a substrate; forming a first insulating layer on the barrier layer; and forming a gate contact, a source contact, and a drain contact on the barrier layer. An interface between the first insulating layer and the barrier layer comprises a modified interface region on a drain access region and/or a source access region of the semiconductor structure such that a sheet resistance of the drain access region and/or the source access region is between 300 and 400 Ω/sq.