H01L29/458

Thin film transistor array substrate and manufacturing method of the same
09831451 · 2017-11-28 · ·

Provided is a thin film transistor array substrate, including a gate electrode, a gate insulating layer covering the gate electrode, a semiconductor pattern formed on the gate insulating layer and including a channel region overlapping the gate electrode, a source electrode and a drain electrode formed on the semiconductor pattern and facing each other with a first opening exposing the channel region therebetween, a first protective layer formed on the gate insulating layer to cover the source electrode, the drain electrode and the semiconductor pattern and a metal oxide layer formed along a surface of the first protective layer.

NICKEL SILICIDE IMPLEMENTATION FOR SILICON-ON-INSULATOR (SOI) RADIO FREQUENCY (RF) SWITCH TECHNOLOGY
20170338321 · 2017-11-23 ·

A radio frequency (RF) switch includes a plurality of series-connected silicon-on-insulator (SOI) CMOS transistors fabricated using a 0.13 micron (or larger) process, wherein the SOI CMOS transistors include nickel silicide formed on the source/drain regions. Each of the series-connected SOI CMOS transistors has a gate length of about 0.13 microns or more, thereby enabling these SOI CMOS transistors to handle high power RF signals, and exhibit the high breakdown voltages required to implement an RF switch. The nickel silicide regions advantageously contribute to a relatively a low on-resistance (R.sub.ON) of the SOI CMOS transistors, while consuming a relatively small amount of the underlying silicon regions during their fabrication. The SOI CMOS transistors can be fabricated on a relatively thin silicon layer, thereby contributing to a relatively low off capacitance (C.sub.OFF) of the SOI CMOS transistors. As a result, an R.sub.ON*C.sub.OFF value of the RF switch is advantageously minimized.

Thin film transistor including diffusion blocking layer and fabrication method thereof, array substrate and display device

A thin film transistor and a fabrication method thereof, an array substrate and a display device are provided. The thin film transistor includes: an active layer, a source-drain metal layer and a diffusion blocking layer located between the active layer and the source-drain metal layer, wherein, the source-drain metal layer includes a source electrode and a drain electrode; the diffusion blocking layer includes a source blocking part corresponding to a position of the source electrode and a drain blocking part corresponding to a position of the drain electrode; and the diffusion blocking layer is doped with different concentrations of nitrogen from a side close to the source-drain metal layer to a side close to the active layer.

Metal Source/Drain Features
20220352339 · 2022-11-03 ·

A semiconductor device according to the present disclosure includes a vertical stack of channel members, a gate structure over and around the vertical stack of channel members, and a first source/drain feature and a second source/drain feature. Each of the vertical stack of channel members extends along a first direction between the first source/drain feature and the second source/drain feature. Each of the vertical stack of channel members is spaced apart from the first source/drain feature by a silicide feature.

Manufacturing method of thin film and metal line for display using the same, thin film transistor array panel, and method for manufacturing the same

A method for forming a thin film according to an exemplary embodiment of the present invention includes forming the thin film at a power density in the range of approximately 1.5 to approximately 3 W/cm.sup.2 and at a pressure of an inert gas that is in the range of approximately 0.2 to approximately 0.3 Pa. This process results in an amorphous metal thin film barrier layer that prevents undesired diffusion from adjacent layers, even when this barrier layer is thinner than many conventional barrier layers.

Manufacutrig method of array substrates, array substrates, and display panels

A manufacturing method of array substrates, an array substrate, and a display panel are disclosed. The manufacturing method of the array substrate includes: forming a first electrode and a gate electrode on a substrate in sequence; forming an insulation layer, a semiconductor layer and a dielectric layer on the substrates in sequence and forming a first through hole, a second through hole and a third through hole; forming a source electrode, a drain electrode, a second electrode and a third electrode on the dielectric layer, wherein the source electrode and the drain electrode connect to the semiconductor layer respectively, the second electrode connects to the first electrode and the third electrode connects with the drain electrode. In this way, the number of the masks needed during the manufacturing process is decreased. In addition, the manufacturing process is simplified and the cost is reduced.

Array substrate, method of fabricating the same, display panel and display device

An array substrate, a method for fabricating the same, a display panel and a display device are disclosed. The array substrate comprises a display area and a non-display area that is outside the display area. The method comprises: forming a metal layer on a base substrate, the metal layer comprising a conductive pattern in the display area and a first electrode in the non-display area; forming a protective layer on the metal layer, a thickness of the protection layer in the non-display area being less than a thickness of the protection layer in the display area; forming a display electrode layer on the protection layer and removing the display electrode layer in the non-display area; and removing the protection layer in the non-display area.

THIN FILM TRANSISTOR AND METHOD THEREOF, ARRAY SUBSTRATE, AND DISPLAY APPARATUS
20170294544 · 2017-10-12 ·

In various embodiments of the disclosed subject matter, a method for forming a thin film transistor (TFT), a related TFT, array substrate, and display apparatus are provided. The method comprises: forming a pattern of an active layer on a base substrate and insulated from a gate electrode; forming a first initial ohmic contacting layer and a second initial ohmic contacting layer on the active layer; forming a source electrode on the first initial ohmic contacting layer, and a drain electrode on the second initial ohmic contacting layer; and performing a heating treatment to the base substrate having the source electrode and the drain electrode thereon, such that metal atoms in the source electrode diffuse to the first initial ohmic contacting layer to form a first ohmic contacting layer, and metal atoms in the drain electrode diffuse to the second initial ohmic contacting layer to form a second ohmic contacting layer.

Memory device and manufacturing method the same

A semiconductor device that can transmit and receive data without contact is popular partly as some railway passes, electronic money cards, and the like; however, it has been a prime task to provide an inexpensive semiconductor device for further popularization. In view of the above current conditions, a semiconductor device of the present invention includes a memory with a simple structure for providing an inexpensive semiconductor device and a manufacturing method thereof. A memory element included in the memory includes a layer containing an organic compound, and a source electrode or a drain electrode of a TFT provided in the memory element portion is used as a conductive layer which forms a bit line of the memory element.

MASK, MANUFACTURING METHOD THEREOF AND EXPOSURE SYSTEM

A mask, including a transparent substrate and mask patterns formed on a surface of the transparent substrate, wherein the mask patterns include a first area for forming film patterns in a display area and a second area for forming film patterns in a non-display area; both the first area and the second area are provided with a plurality of patterned sub-masks; a distribution density of the patterned sub-masks in the first area is less than a distribution density of the patterned sub-masks in the second area; each patterned sub-mask includes a first pattern for forming a source electrode of a transistor, a second pattern for forming a drain electrode of the transistor, and a slit interposed between the first pattern and the second pattern; and a width of the slit in the first area is greater than a width of the slit in the second area.