In an electro-optical device, a transistor includes a semiconductor layer extending in a second direction so as to overlap with a scanning line in plan view. A second contact hole for electrically connecting the scanning line with a gate electrode of the transistor is provided in a second interlayer insulating layer provided in a layer between the scanning line and the transistor. The second contact hole includes a first hole portion extending along the second direction on both sides of the semiconductor layer in plan view, and a second hole portion protruding from the first hole portion toward the semiconductor layer and extending along a first direction.

A semiconductor structure includes at least two field effect transistors. A gate strip including a plurality of gate dielectrics and a gate electrode strip can be formed over a plurality of semiconductor active regions. Source/drain implantation is conducted using the gate strip as a mask. The gate strip is divided into gate electrodes after the implantation.

A semiconductor structure includes at least two field effect transistors. A gate strip including a plurality of gate dielectrics and a gate electrode strip can be formed over a plurality of semiconductor active regions. Source/drain implantation is conducted using the gate strip as a mask. The gate strip is divided into gate electrodes after the implantation.

A semiconductor structure includes at least two field effect transistors. A gate strip including a plurality of gate dielectrics and a gate electrode strip can be formed over a plurality of semiconductor active regions. Deep source/drain regions are formed by implanting dopants into semiconductor active regions without implanting the dopants into inter-electrode regions of a shallow trench isolation structure. The gate strip is divided into gate stacks prior to or after formation of the deep source/drain regions.

A semiconductor device includes a region of semiconductor material comprising a shielded-gate trench structure. The shielded-gate trench structure includes an active trench, an insulated shield electrode in the lower portion of the active trench, an insulated gate electrode adjacent to the gate dielectric in an upper portion of the active trench, and an inter-pad dielectric (IPD) interposed between the gate electrode and the shield electrode. A conductive region is within the active trench and extends through the gate electrode and the IPD and is electrically connected to the shield electrode. The conductive region is electrically isolated from the gate electrode. The gate electrode comprises a shape that is uninterrupted on at least one side the conductive region in a top view so that the gate electrode.

An embodiment of a method of integration of a non-volatile memory device into a logic MOS flow is described. Generally, the method includes: forming a pad dielectric layer of a MOS device above a first region of a substrate; forming a channel of the memory device from a thin film of semiconducting material overlying a surface above a second region of the substrate, the channel connecting a source and drain of the memory device; forming a patterned dielectric stack overlying the channel above the second region, the patterned dielectric stack comprising a tunnel layer, a charge-trapping layer, and a sacrificial top layer; simultaneously removing the sacrificial top layer from the second region of the substrate, and the pad dielectric layer from the first region of the substrate; and simultaneously forming a gate dielectric layer above the first region of the substrate and a blocking dielectric layer above the charge-trapping layer.

A gate structure in a semiconductor device includes: a gate stack formed on a substrate with three sections, a bottom portion, a top portion, and a sacrificial cap layer over the top portion; gate spacers, source and drain regions, a nitride encapsulation over top and sidewalls of the gate stack after removal of the sacrificial cap layer, an organic planarizing layer over the nitride encapsulation, planarizing the encapsulation, and silicidation performed over the source and drain regions and the bottom portion after removal of the nitride encapsulation, the organic planarizing layer, and the top portion of the gate stack.

A semiconductor device according to an embodiment, includes: a silicon carbide layer; a gate electrode; and a gate insulating layer, the gate electrode including a p-type silicon carbide region containing aluminum, the gate insulating layer having a first region and a second region, the first region including a silicon oxide or a silicon oxynitride, the second region being positioned between the first region and the gate electrode, the second region including an oxide containing aluminum.

A method for fabricating a Fin-FET includes forming a plurality of fin structures, an isolation layer, and an interlayer dielectric layer on an NMOS region of a substrate, forming a first opening in the interlayer dielectric layer to expose a portion of the fin structures. A region adjacent to a joint between a bottom surface and a sidewall surface of the first opening is a corner region. The method includes forming a high-k dielectric layer on the bottom and the sidewall surfaces of the first opening, a barrier layer on the high-k dielectric layer, and an N-type work function layer containing aluminum ions on the barrier layer. The method further includes performing a back-flow annealing process such that the portion of N-type work function layer at the corner region is thickened and contains diffused aluminum ions. Finally, the method includes forming a metal layer on the N-type work function layer.

A semiconductor device includes a substrate. The semiconductor device further includes a first polysilicon structure over the substrate, wherein the first polysilicon structure has a first grain size. The semiconductor device further includes a first barrier layer over the first polysilicon structure, wherein the first barrier layer has a non-uniform thickness. The semiconductor device further includes a second polysilicon structure over the first barrier layer, wherein the second polysilicon structure has a second grain size smaller than the first grain size.