A method includes forming a gate trench over a semiconductor fin. The gate trench includes an upper portion surrounded by first gate spacers and a lower portion surrounded by second gate spacers and the first gate spacers. The method includes forming a metal gate in the lower portion of the gate trench. The metal gate is disposed over a first portion of a gate dielectric layer. The method includes depositing a metal material in the gate trench to form a gate electrode overlaying the metal gate in the lower portion of the gate trench, while keeping sidewalls of the first gate spacers and upper surfaces of the second gate spacer overlaid by a second portion of the gate dielectric layer. The method includes removing the second portion of the gate dielectric layer, while remaining the gate electrode substantially intact.

A method for fabricating a semiconductor component includes forming an interlayer dielectric (ILD) layer on a substrate, forming a trench in the interlayer dielectric layer, forming a metal gate in the trench, removing a portion of the metal gate protruding from the ILD layer, reacting a reducing gas with the metal gate, and removing a top portion of the metal gate.

Provided are a method for manufacturing a thin-film transistor (TFT) substrate and a TFT substrate. The method for manufacturing a TFT substrate is capable of effectively protecting the surface of the inorganic insulating layer in the mark area and the mark peripheral area during performing dry etching on the metal layer by providing a protective layer between the inorganic insulating layer and the metal layer to reduce the surface damage of the inorganic insulating layer during dry etching, thereby effectively improving the recognition rate of the alignment mark by the CCD camera in the subsequent alignment process, improving the alignment detection accuracy, and avoiding subsequent alignment anomalies. In addition, it is not necessary to adjust the dry etching parameters of the metal layer, which indirectly reduces the process constraints of the dry etching process, avoids modification and calibration of the alignment CCD camera, and lowers production costs.

A method includes forming a gate trench over a semiconductor fin. The gate trench includes an upper portion surrounded by first gate spacers and a lower portion surrounded by second gate spacers and the first gate spacers. The method includes forming a metal gate in the lower portion of the gate trench. The metal gate is disposed over a first portion of a gate dielectric layer. The method includes depositing a metal material in the gate trench to form a gate electrode overlaying the metal gate in the lower portion of the gate trench, while keeping sidewalls of the first gate spacers and upper surfaces of the second gate spacer overlaid by a second portion of the gate dielectric layer. The method includes removing the second portion of the gate dielectric layer, while remaining the gate electrode substantially intact.

Provided are a method for manufacturing a thin-film transistor (TFT) substrate and a TFT substrate. The method for manufacturing a TFT substrate is capable of effectively protecting the surface of the inorganic insulating layer in the mark area and the mark peripheral area during performing dry etching on the metal layer by providing a protective layer between the inorganic insulating layer and the metal layer to reduce the surface damage of the inorganic insulating layer during dry etching, thereby effectively improving the recognition rate of the alignment mark by the CCD camera in the subsequent alignment process, improving the alignment detection accuracy, and avoiding subsequent alignment anomalies. In addition, it is not necessary to adjust the dry etching parameters of the metal layer, which indirectly reduces the process constraints of the dry etching process, avoids modification and calibration of the alignment CCD camera, and lowers production costs.

A semiconductor device includes a nanosheet device and a gate-all-around FIN-shaped (GAA-FIN) device. The nanosheet device includes n- and p-type field effect transistor (nFET and pFET) sections, each of which includes nanosheet stacks and work function metal (WFM). Each nanosheet stack includes lowermost and uppermost spacers, intermediate semiconductor layers and dielectric material surrounding the lowermost and uppermost spacers and the intermediate semiconductor layers. The WFM surrounds the nanosheet stacks and entirely fills suspension regions thereof. The GAA-FIN device includes nFET and pFET sections, each of which includes fin elements and WFM. Each fin element includes a lower spacer, a secondary intermediate layer of semiconductor material and dielectric material surrounding the lower spacer and the secondary intermediate layer of semiconductor material. The WFM surrounds each of the fin elements. A thickness of the WFM entirely filling the suspension regions exceeds a thickness of the WFM of the fin elements.

A method includes forming a gate stack, which includes a gate dielectric and a metal gate electrode over the gate dielectric. An inter-layer dielectric is formed on opposite sides of the gate stack. The gate stack and the inter-layer dielectric are planarized. The method further includes forming an inhibitor film on the gate stack, with at least a portion of the inter-layer dielectric exposed, selectively depositing a dielectric hard mask on the inter-layer dielectric, with the inhibitor film preventing the dielectric hard mask from being formed thereon, and etching to remove a portion of the gate stack, with the dielectric hard mask acting as a portion of a corresponding etching mask.

A semiconductor having a first gate-all-around (GAA) transistor, a second GAA transistor, and a third GAA transistor is provided. The first (GAA) transistor includes a first plurality of channel members, a gate dielectric layer over the first plurality of channel members, a first work function layer over the gate dielectric layer, and a glue layer over the first work function layer. The second GAA transistor include a second plurality of channel members, the gate dielectric layer over the second plurality of channel members, and a second work function layer over the gate dielectric layer, the first work function layer over and in contact with the second work function layer, and the glue layer over the first work function layer. The third GAA transistor includes a third plurality of channel members, the gate dielectric layer over the third plurality of channel members, and the glue layer over the gate dielectric layer.

The present disclosure provides a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes a substrate, a word line, a plurality of first impurity regions, a second impurity region, and an isolation film. The word line is W-shaped, is disposed in the substrate, and includes a base and a pair of legs connected to the base. The first impurity regions are disposed in the substrate and on either side of the word line. The second impurity region is disposed between the legs of the word line. The isolation film is disposed in the substrate, wherein the word line is surrounded by the isolation film.

A semiconductor device includes a substrate, a first gate structure, a plurality of first gate spacers, a second gate structure, and a plurality of second gate spacers. The substrate has a first fin structure and a second fin structure. The first gate structure is over the first fin structure, in which the first gate structure includes a first high dielectric constant material and a first metal. A bottom surface of the first high dielectric constant material is higher than bottom surfaces of the first gate spacers. The second gate structure is narrower than the first gate structure and over the second fin structure, in which the second gate structure includes a second high dielectric constant material and a second metal. A bottom surface of the second high dielectric constant material is lower than bottom surfaces of the second gate spacers.