Incorporation of metallic quantum dots (e.g., silver bromide (AgBr) films) into the source and drain regions of a MOSFET can assist in controlling the transistor performance by tuning the threshold voltage. If the silver bromide film is rich in bromine atoms, anion quantum dots are deposited, and the AgBr energy gap is altered so as to increase V.sub.t. If the silver bromide film is rich in silver atoms, cation quantum dots are deposited, and the AgBr energy gap is altered so as to decrease V.sub.t. Atomic layer deposition (ALD) of neutral quantum dots of different sizes also varies V.sub.t. Use of a mass spectrometer during film deposition can assist in varying the composition of the quantum dot film. The metallic quantum dots can be incorporated into ion-doped source and drain regions. Alternatively, the metallic quantum dots can be incorporated into epitaxially doped source and drain regions.

Integrated circuits and methods of producing the same are provided herein. In accordance with an exemplary embodiment, an integrated circuit includes an SOI substrate with an active layer overlying a buried insulator layer that in turn overlies a handle layer. A source is defined within the active layer, and a gate well is also defined within the active layer. A first ultra shallow trench isolation extends into the active layer, where a first portion of the active layer is positioned between the first ultra shallow trench isolation and the buried insulator layer. The first ultra shallow trench isolation is positioned between the source and the gate well.

Some embodiments include a NAND memory array having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include terminal regions, and include nonterminal regions proximate the terminal regions. The terminal regions are vertically thicker than the nonterminal regions, and are configured as segments which are vertically stacked one atop another and which are vertically spaced from one another. Blocks are adjacent to the segments and have approximately a same vertical thickness as the segments. The blocks include high-k dielectric material, charge-blocking material and charge-storage material. Channel material extends vertically along the stack and is adjacent to the blocks. Some embodiments include integrated assemblies. Some embodiments include methods of forming integrated assemblies.

A semiconductor device in which sufficient stress can be applied to a channel region due to lattice constant differences.

In a method of manufacturing a semiconductor device, first and second gate structures are formed. The first (second) gate structure includes a first (second) gate electrode layer and first (second) sidewall spacers disposed on both side faces of the first (second) gate electrode layer. The first and second gate electrode layers are recessed and the first and second sidewall spacers are recessed, thereby forming a first space and a second space over the recessed first and second gate electrode layers and first and second sidewall spacers, respectively. First and second protective layers are formed in the first and second spaces, respectively. First and second etch-stop layers are formed on the first and second protective layers, respectively. A first depth of the first space above the first side wall spacers is different from a second depth of the first space above the first gate electrode layer.

A high voltage metal-oxide-semiconductor laterally diffused device (HV LDMOS), and more particularly an insulated gate bipolar junction transistor (IGBT), is disclosed. The device includes a semiconductor substrate, a gate structure formed on the substrate, a source and a drain formed in the substrate on either side of the gate structure, a first doped well formed in the substrate, and a second doped well formed in the first well. The gate, source, second doped well, a portion of the first well, and a portion of the drain structure are surrounded by a deep trench isolation feature and an implanted oxygen layer in the silicon substrate.

A method for fabricating a nanowire transistor is disclosed. First, a substrate is provided, and a stack structure is formed on the substrate, in which the stack structure includes a first semiconductor layer and a second semiconductor layer and the first semiconductor layer and the second semiconductor layer are made of different material. Next, a hard mask is formed on the stack structure and a first spacer adjacent to the hard mask, part of the stack structure is removed; a second spacer is formed adjacent to the first spacer and the stack structure; and a source/drain structure is formed adjacent to two sides of the second spacer.

A semiconductor device includes a silicon-on-insulator (SOI) substrate having a stack of a first semiconductor substrate, a buried insulating layer and a second semiconductor substrate formed in a first region and a deep trench isolation disposed in a second region. The method of forming the semiconductor device includes providing a SOI substrate having shallow trench isolations (STIs) and transistors formed within and on the second semiconductor substrate, respectively. The method also includes forming a hard mask over the first region and removing the STIs, the transistors, the second semiconductor substrate and the buried insulating layer in the second region using the hard mask as a mask, and forming a capping layer covering the deep trench isolation and the second semiconductor substrate including the transistors.

A transistor includes a substrate and a gate over the substrate. The transistor further includes a source and a drain over the substrate on opposite sides of the gate. The transistor further includes a channel region beneath the gate separating the source from the drain, the channel region having a channel width with respect to a surface of the substrate greater than a width of the gate with respect to the surface of the substrate. The transistor further includes a silicide over a first portion of the drain, wherein a second portion of the drain, closer to the gate than the first portion, is an unsilicided region.

A semiconductor device has a silicide source/drain region is fabricated by growing silicon on an epitaxial region including silicon and either germanium or carbon. In the method, a gate electrode is formed on a semiconductor substrate with a gate insulating layer interposed therebetween. An epitaxial layer is formed in the semiconductor substrate at both sides of the gate electrodes. A silicon layer is formed to cap the epitaxial layer. The silicon layer and a metal material are reacted to form a silicide layer. In a PMOS, the epitaxial layer has a top surface and inclined side surfaces that are exposed above the upper surface of the active region. The silicon layer is grown on the epitaxial layer in such a way as to cap the top and inclined surfaces.