A structure includes a first dielectric over a trench silicide (TS) contact and over a gate structure, and at least one cavity in the first dielectric. A metal resistor layer is on a bottom and sidewalls of the at least one cavity and extends over the first dielectric. A first contact is on the metal resistor layer over the first dielectric; and a second contact is on the metal resistor layer over the first dielectric. The metal resistor layer is over the TS contact and over the gate structure. Where a plurality of cavities are provided in the dielectric, a resistor structure formed by the metal resistor layer may have an undulating cross-section over the plurality of cavities and the dielectric.

In a semiconductor device being fabricated, a gate structure, a first source/drain (S/D) structure, and a second S/D structure are formed. A first spacer of a first dielectric material is formed between the gate structure and the first S/D structure. A second spacer is formed between the gate structure and the second S/D structure, such that a first gap is created within a second dielectric material of the second spacer.

A semiconductor device includes a semiconductor substrate, multiple trench gate structures and an emitter region. The semiconductor substrate includes: a drift layer of a first conductivity type; a base layer of a second conductivity type disposed on the drift layer; and a collector layer of the second conductivity type, the collector layer disposed at a position opposite to the base layer with the drift layer sandwiched between the base layer and the collector layer. Each of the trench gate structures includes: a trench penetrating the base layer and reaching the drift layer; a gate insulation film is disposed at a wall surface of the trench; and a gate electrode disposed on the gate insulation film. The emitter region is disposed on a surface layer portion of the base layer and is in contact with the trench.

Structures for a microfluidic channel and methods of forming a structure for a microfluidic channel. The structure comprises a trench in a semiconductor substrate and a semiconductor layer inside the trench. The trench has an entrance and a sidewall extending from the entrance into the semiconductor substrate. The semiconductor layer has a first portion surrounding a portion of the trench to define a cavity and a second portion positioned to obstruct the entrance to the trench. The second portion of the semiconductor layer is thicker than the first portion of the semiconductor layer.

A manufacturing method of a semiconductor device includes forming a plurality of flash memory structures on a semiconductor substrate, wherein each of the flash memory structures includes a floating gate formed on the semiconductor substrate and a control gate formed on the floating gate; forming at least one pseudo contact between the plurality of flash memory structures; forming a liner film conformally on a surface of the pseudo contact; forming an interlayer dielectric layer on the whole semiconductor substrate to cover the pseudo contact and form at least one air gap between the pseudo contact and the flash memory structure; planarizing the interlayer dielectric layer until the top of the pseudo contact is exposed; removing the pseudo contact to form a contact opening; and forming a conductive material in the contact opening.

A method for fabricating a semiconductor structure includes providing a base substrate, including a substrate, a plurality of gate structures formed on the substrate, and a cap layer formed on the plurality of gate structures; removing the cap layer to form a trench on each gate structure; and forming a substitution layer in the trench. The dielectric constant of the substitution layer is smaller than the dielectric constant of the cap layer.

A manufacturing method of a semiconductor device includes forming a plurality of flash memory structures on a semiconductor substrate, wherein each of the flash memory structures includes a floating gate formed on the semiconductor substrate and a control gate formed on the floating gate; forming at least one pseudo contact between the plurality of flash memory structures; forming a liner film conformally on a surface of the pseudo contact; forming an interlayer dielectric layer on the whole semiconductor substrate to cover the pseudo contact and form at least one air gap between the pseudo contact and the flash memory structure; planarizing the interlayer dielectric layer until the top of the pseudo contact is exposed; removing the pseudo contact to form a contact opening; and forming a conductive material in the contact opening.

A semiconductor structure is provided in which an L-shaped airgap spacer is located between a functional gate structure and a source/drain contact structure. The L-shaped airgap spacer is sandwiched between a lower dielectric material spacer that is L-shaped and an upper dielectric material spacer that is also L-shaped.

The present disclosure relates to semiconductor structures and, more particularly, to cavity structures under shallow trench isolation regions and methods of manufacture. The structure includes: one or more cavity structures provided in a substrate material and sealed with an epitaxial material; and a shallow trench isolation region directly above the one or more cavity structures in the substrate material.

A method of scaling a nonvolatile trapped-charge memory device and the device made thereby is provided. In an embodiment, the method includes forming a channel region including polysilicon electrically connecting a source region and a drain region in a substrate. A tunneling layer is formed on the substrate over the channel region by oxidizing the substrate to form an oxide film and nitridizing the oxide film. A multi-layer charge trapping layer including an oxygen-rich first layer and an oxygen-lean second layer is formed on the tunneling layer, and a blocking layer deposited on the multi-layer charge trapping layer. In one embodiment, the method further includes a dilute wet oxidation to densify a deposited blocking oxide and to oxidize a portion of the oxygen-lean second layer.