In a semiconductor device being fabricated, a gate structure, a first source/drain (S/D) structure, and a second S/D structure are formed. A first spacer of a first dielectric material is formed between the gate structure and the first S/D structure. A second spacer is formed between the gate structure and the second S/D structure, such that a first gap is created within a second dielectric material of the second spacer.

The present disclosure relates to semiconductor structures and, more particularly, to sealed cavity structures having a planar surface and methods of manufacture. The structure includes a cavity formed in a substrate material and which has a curvature at its upper end. The cavity is covered with epitaxial material that has an upper planar surface.

A method is presented for employing contact over active gate to reduce parasitic capacitance. The method includes forming high-k metal gates (HKMGs) between stacked spacers, the stacked spacers including a low-k dielectric lower portion and a sacrificial upper portion, forming a first dielectric over the HKMGs, forming first contacts to source/drain of a transistor between the HKMGs, and forming a second dielectric over the first contacts. The method further includes selectively removing the first dielectric to form second contacts to the HKMGs, selectively removing the second dielectric to form third contacts on top of the first contacts, removing the sacrificial upper portion of the stacked spacers, and depositing a third dielectric that pinches off the remaining first and second dielectrics to form air-gaps between the first contacts and the HKMGs.

According to an embodiment, a method of manufacturing a semiconductor device includes forming a semiconductor layer having a first conductivity type on a semiconductor substrate, forming a trench in the semiconductor substrate and the semiconductor layer, forming a semiconductor film having a second conductivity type on an inner wall surface and a bottom surface of the trench, forming a first insulating film including silicon oxide on a side surface and a bottom surface of the semiconductor film, forming a second insulating film including silicon nitride on a side surface and a bottom surface of the first insulating film, and forming a third insulating film including silicon oxide on a side surface and a bottom surface of the second insulating film.

Semiconductor devices and methods are provided to fabricate FET devices. For example, a semiconductor device can include a functional gate structure on a channel region of a fin structure; and a source/drain region on each side of the functional gate structure. The functional gate structure has an insulator material abutting a portion of the sidewalls of the functional gate structure and the source drain region and the top surface of the fin. The functional gate structure further includes a dielectric top layer. The dielectric top layer seals an air gap between the top surface of the insulator material and the dielectric top layer.

Semiconductor devices and methods are provided to fabricate FET devices. For example, a semiconductor device can include a functional gate structure on a channel region of a fin structure; and a source/drain region on each side of the functional gate structure. The functional gate structure has an insulator material abutting a portion of the sidewalls of the functional gate structure and the source drain region and the top surface of the fin, with a top surface of the insulator material in contact with a bottom surface of the first spacer layer. The functional gate structure further includes a dielectric top layer. The dielectric top layer seals an air gap between the top surface of the insulator material and the dielectric top layer.

A semiconductor device includes a substrate, a gate structure, a spacer, a mask layer, and at least one void. The gate structure is disposed on the substrate, and the gate structure includes a metal gate electrode. The spacer is disposed on sidewalls of the gate structure, and a topmost surface of the spacer is higher than a topmost surface of the metal gate electrode. The mask layer is disposed on the gate structure. At least one void is disposed in the mask layer and disposed between the metal gate electrode and the spacer.

A semiconductor structure includes a first device and a second device. The first device includes: a first gate structure formed over an active region and a first air spacer disposed adjacent to the first gate structure. The second device includes: a second gate structure formed over an isolation structure and a second air spacer disposed adjacent to the second gate structure. The first air spacer and the second air spacer have different sizes.

The present disclosure relates to semiconductor structures and, more particularly, to sealed cavity structures having a planar surface and methods of manufacture. The structure includes a cavity formed in a substrate material and which has a curvature at its upper end. The cavity is covered with epitaxial material that has an upper planar surface.

Semiconductor devices and methods are provided to fabricate FET devices. For example, a semiconductor device can include a functional gate structure on a channel region of a fin structure; and a source/drain region on each side of the functional gate structure. The functional gate structure has an insulator material abutting a portion of the sidewalls of the functional gate structure and the source drain region and the top surface of the fin, with a top surface of the insulator material in contact with a bottom surface of the first spacer layer. The functional gate structure further includes a dielectric top layer. The dielectric top layer seals an air gap between the top surface of the insulator material and the dielectric top layer.