A method for forming a semiconductor device. In this method, a semiconductor fin is formed on a semiconductor substrate. Two cells adjacent to each other are formed on the semiconductor fin. A gate conductor is formed on a top of the semiconductor fin at a common boundary that is shared by the two cells. A gate spacer is formed to peripherally enclose the gate conductor. The gate conductor and the semiconductor fin are etched to form an air gap, thereby dividing the semiconductor fin into two portions of the semiconductor fin. A dielectric cap layer is deposited into the air gap to cap a top of the air gap.

A semiconductor device that includes a gate structure on a channel region of a semiconductor device. Source and drain regions may be present on opposing sides of the channel region. The semiconductor device may further include a composite gate sidewall spacer present on a sidewall of the gate structure. The composite gate sidewall spacer may include a first composition portion having an air gap encapsulated therein, and a second composition portion that is entirely solid and present atop the first composition portion.

A semiconductor device and a method for fabricating the semiconductor device are provided. The method includes providing a semiconductor substrate including a first region and a second region, and forming a plurality of fins on the semiconductor substrate in the first region and the second region. The method also includes forming a first barrier layer on surfaces of the fins in the first region, and forming an isolation fluid layer on the semiconductor substrate to cover the first barrier layer in the first region and to cover the fins in the second region. Further, the method includes forming an isolation film and a by-product layer by an oxygen-containing annealing process respectively from the isolation fluid layer and sidewalls of the fins in the second region.