A method includes removing a dummy gate stack to form a first trench between gate spacers, forming a replacement gate stack in the first trench, recessing the replacement gate stack to form a second trench between the gate spacers, selectively depositing a conductive capping layer in the second trench, forming a dielectric hard mask in the second trench and over the conductive capping layer, and etching the dielectric hard mask using an etching gas to form an opening in the dielectric hard mask. The replacement gate stack is revealed to the opening. The conductive capping layer is more resistant to the etching gas than the replacement gate stack. The method further comprises forming a gate contact plug over and contacting the conductive capping layer.

A method for manufacturing a pressure sensitive transistor includes forming a channel region between first and second contact regions in a semiconductor substrate, forming a first isolation layer on a surface of the semiconductor substrate, forming a sacrificial structure on the first isolation layer and above the channel region, forming a semiconductor layer on the sacrificial structure and on the first isolation layer, wherein the semiconductor layer covers the sacrificial structure, removing the sacrificial structure for providing a cavity between the substrate and the semiconductor layer, wherein the semiconductor layer forms a membrane structure and forms a control electrode of the pressure sensitive transistor, forming a second isolation layer on the membrane structure and on the exposed portion of the surface of the semiconductor substrate, and forming contacting structures for the first contact region, the second contact region and the membrane structure of the pressure sensitive transistor.

A flash memory device includes a substrate, a plurality of active regions and a plurality of first isolation regions alternately arranged in a first direction and extending in a second direction different from the first direction, a plurality of gate structures on the substrate, the gate structures being spaced apart from each other and extending in the second direction, a gap structure between the gate structures, and a second isolation region filling an upper portion of the gap structure and leaving a first air gap in a lower portion of the gap structure.

The present disclosure provides a method of fabricating a semiconductor structure in accordance with some embodiments. The method includes receiving a substrate having an active region and an isolation region; forming gate stacks on the substrate and extending from the active region to the isolation region; forming an inner gate spacer and an outer gate spacer on sidewalls of the gate stacks; forming an interlevel dielectric (ILD) layer on the substrate; removing the outer gate spacer in the isolation region, resulting in an air gap between the inner gate spacer and the ILD layer; and performing an ion implantation process to the ILD layer, thereby expanding the ILD layer to cap the air gap.

Disclosed is a semiconductor device for improving a gate induced drain leakage and a method for fabricating the same, and the method may include forming a trench in a substrate, lining a surface of the trench with an initial gate dielectric layer, forming a gate electrode to partially fill the lined trench, forming a sacrificial material spaced apart from a top surface of the gate electrode and to selectively cover a top corner of the lined trench, removing a part of the initial gate dielectric layer of the lined trench which is exposed by the sacrificial material in order to form an air gap, and forming a capping layer to cap a side surface of the air gap, over the gate electrode.

A method of forming a semiconductor structure includes following steps. A first isolation is formed between a pair of active regions. A gate structure is formed on the first isolation structure. The active regions are etched to form recesses with curved top surfaces. The active regions are etched again to change each of the curved top surfaces to be a top surface and a sidewall substantially perpendicular to the top surface. A pair of contacts is formed respectively on the active regions, such that each of the contacts has a bottom surface and a sidewall substantially perpendicular to the bottom surface.

The present disclosure describes a method for forming gate spacer structures with air-gaps to reduce the parasitic capacitance between the transistor's gate structures and the source/drain contacts. In some embodiments, the method includes forming a gate structure on a substrate and a spacer stack on sidewall surfaces of the gate structure where the spacer stack comprises an inner spacer layer in contact with the gate structure, a sacrificial spacer layer on the inner spacer layer, and an outer spacer layer on the sacrificial spacer layer. The method further includes removing the sacrificial spacer layer to form an opening between the inner and outer spacer layers, depositing a polymer material on top surfaces of the inner and outer spacer layers, etching top sidewall surfaces of the inner and outer spacer layers to form a tapered top portion, and depositing a seal material.

Provided are a solid-state image-capturing element and an electronic device capable of reducing the capacitance by using a hollow region. At least a part of a region between an FD wiring connected to a floating diffusion and a wiring other than the FD wiring is a hollow region. The present disclosure can be applied to a CMOS image sensor having, for example, a floating diffusion, a transfer transistor, an amplifying transistor, a selection transistor, a reset transistor, and a photodiode.

A method includes forming a gate stack over a semiconductor region, and forming a first gate spacer on a sidewall of the gate stack. The first gate spacer includes an inner sidewall spacer, and a dummy spacer portion on an outer side of the inner sidewall spacer. The method further includes removing the dummy spacer portion to form a trench, and forming a dielectric layer to seal a portion of the trench as an air gap. The air gap and the inner sidewall spacer in combination form a second gate spacer. A source/drain region is formed to have a portion on an outer side of the second gate spacer.

A method of manufacturing a semiconductor device having a super junction structure, includes: forming a first-conductivity-type semiconductor layer having a first surface and a second surface opposite to the first surface; forming a second-conductivity-type pillar region in the semiconductor layer; forming an insulating layer which covers the second surface of the semiconductor layer; forming a metal layer on the insulating layer; forming a gate electrode including a first opening passing through the metal layer by selectively removing the metal layer; and etching the insulating layer via the first opening, wherein the etching the insulating layer includes partially exposing the semiconductor layer by forming a second opening having a curved sidewall in the insulating layer by isotropic etching, and wherein an exposed surface of the semiconductor layer forms a flat surface continuous with the second surface of the semiconductor layer covered with the insulating layer.