Disclosed is a semiconductor device for improving a gate induced drain leakage and a method for fabricating the same, and the semiconductor device includes a substrate, a first doped region and a second doped region formed to be spaced apart from each other by a trench in the substrate, a first gate dielectric layer over the trench, a lower gate over the first gate dielectric layer, an upper gate over the lower gate and having a smaller width than the lower gate, and a second gate dielectric layer between the upper gate and the first gate dielectric layer.

A semiconductor device includes a transistor. The transistor includes a gate electrode, a channel layer, a gate dielectric layer, a first source/drain region and a second source/drain region and a first spacer. The channel layer is disposed on the gate electrode. The gate dielectric layer is located between the channel layer and the gate electrode. The first source/drain region and the second source/drain region are disposed on the channel layer at opposite sides of the gate electrode, and at least one of the first and second source/drain regions includes a first portion and a second portion between the first portion and the gate electrode. The first spacer is disposed on the channel layer. The first spacer is disposed on a first sidewall of the second portion of the at least one of the first and second source/drain regions, and the first portion is disposed on the first spacer.

A method used in forming an electronic component comprising conductive material and ferroelectric material comprises forming a non-ferroelectric metal oxide-comprising insulator material over a substrate. A composite stack comprising at least two different composition non-ferroelectric metal oxides is formed over the substrate. The composite stack has an overall conductivity of at least 1×10.sup.2 Siemens/cm. The composite stack is used to render the non-ferroelectric metal oxide-comprising insulator material to be ferroelectric. Conductive material is formed over the composite stack and the insulator material. Ferroelectric capacitors and ferroelectric field effect transistors independent of method of manufacture are also disclosed.

A FeFET configured as a 2-bit storage device that includes a gate stack including a ferroelectric layer over a semiconductor substrate; and the ferroelectric layer includes dipoles; and a first set of dipoles at the first end of the ferroelectric layer has a first polarization; and a second set of dipoles at the second end of the ferroelectric layer has a second polarization, the first and second polarizations of the corresponding first and second sets of dipoles representing storage of 2 bits, wherein a first bit of the 2-bit storage device being configured to be read by application of a read voltage to the source region and a do-not-disturb voltage to the drain region; and a second bit of the 2-bit storage device being configured to be read by application of the do-not-disturb voltage to the source region and the read voltage to the drain region.

Provided is a thin film structure including a substrate, a metal layer on the substrate and spaced apart from the substrate, and a two-dimensional material layer between the substrate and the metal layer. The two-dimensional material layer may be configured to limit and/or block an electron transfer between the substrate and the metal layer. A resistivity of a metal layer on the two-dimensional material layer may be lowered by the two-dimensional material layer.

A semiconductor device includes a substrate, a first insulating layer on the substrate, source and drain patterns at spaced-apart locations on the first insulating layer, and a channel layer having a transition metal therein, such as a transition metal dichalcogenide. The channel layer extends on the first insulating layer and between the source and drain patterns. A second insulating layer is also provided, which extends on the channel layer and has a thickness less than a thickness of the first insulating layer. A gate structure is provided, which extends on the second insulating layer, and opposite the channel layer. The channel layer may include at least one of MoS.sub.2, WS.sub.2, MoSe.sub.2, WSe.sub.2, MoSe.sub.2, WTe.sub.2, and ZrSe.sub.2.

A ferroelectric memory device includes interlayer insulating layers and gate lines alternately stacked, a data storage layer vertically passing through the interlayer insulating layers and the gate lines and having a cylindrical shape, and a channel layer formed in an area enclosed by the data storage layer. The data storage layer includes a first ferroelectric layer abutting on the channel layer, a second ferroelectric layer abutting on the interlayer insulating layers and the gate lines, and an interface layer formed between the first and the second ferroelectric layers.

The disclosed technology generally relates to memory structures, for example for a vertical NAND memory. In one aspect, a memory structure includes a substrate and a layer stack arranged on a surface of the substrate, wherein the layer stack includes one or more conductive material layers alternating with one or more dielectric material layers. The memory structure can also include a trench in the layer stack, wherein the trench is formed through the one or more conductive material layers, and wherein the trench includes inner side walls. The memory structure also includes a programmable material layer arranged in the trench and which covers the inner side walls of the trench. The memory structure further includes an oxide semiconductor layer arranged in the trench over the programmable material layer.

An electronic device includes: a substrate including a source, a drain, and a channel between the source and the drain; a gate electrode arranged above the substrate and facing the channel, the gate electrode being apart from the channel in a first direction; and a ferroelectric thin film structure between the channel and the gate electrode, the ferroelectric thin film structure including a first ferroelectric layer, a crystallization barrier layer including a dielectric material, and a second ferroelectric layer, which are sequentially arranged from the channel in the first direction. The average of sizes of crystal grains of the first ferroelectric layer may be less than or equal to the average of sizes of crystal grains of the second ferroelectric layer, and owing to small crystal grains, dispersion of performance may be improved.

In a method of manufacturing a negative capacitance structure, a dielectric layer is formed over a substrate. A first metallic layer is formed over the dielectric layer. After the first metallic layer is formed, an annealing operation is performed, followed by a cooling operation. A second metallic layer is formed. After the cooling operation, the dielectric layer becomes a ferroelectric dielectric layer including an orthorhombic crystal phase.