A ferroelectric thin-film structure includes at least one first atomic layer and at least one second atomic layer. The first atomic layer includes a first dielectric material that is based on an oxide, and the second atomic layer includes both the first dielectric material and a dopant that has a bandgap greater than a bandgap of the dielectric material.

A ferroelectric memory device includes a multi-layer stack, a channel layer and a III-V based ferroelectric layer. The multi-layer stack is disposed on a substrate and includes a plurality of conductive layers and a plurality of dielectric layers stacked alternately. The channel layer penetrates through the plurality of conductive layers and the plurality of dielectric layers of the multi-layer stack. The III-V based ferroelectric layer is disposed between the channel layer and the multi-layer stack, and includes at least one element selected from Group III elements, at least one element selected from Group V elements, and at least one element selected from transition metal elements.

A semiconductor device includes an active pattern which includes a lower pattern extending in a first direction, and sheet patterns spaced apart from the lower pattern in a second direction perpendicular to an upper surface of the lower pattern, each sheet pattern including an upper surface and a lower surface, a gate structure disposed on the lower pattern and including a gate electrode and a gate insulating film, the gate electrode and the gate insulating film surrounding each sheet pattern, and a source/drain pattern disposed on at least one side of the gate structure. The gate structure includes inter-gate structures that are disposed between the lower pattern and a lowermost sheet pattern and between two sheet patterns, and contacts the source/drain pattern. The gate insulating film includes a horizontal portion with a first thickness, and a first vertical portion with a second thickness different from the first thickness.

Provided are a ferroelectric material and an electronic device including same, the ferroelectric material including: a first domain including a first polarization layer which is polarized in a first direction and a first spacer layer disposed adjacent to the first polarization layer; a second domain including a second polarization layer which is polarized in a second direction distinct from the first direction and a second spacer layer disposed adjacent to the second polarization layer; and a structural layer, which is disposed at a domain wall between the first domain and the second domain, and belongs to/has atoms arranged according to a Pbcn space group.

A method for manufacturing a semiconductor device, the method including forming a fin type pattern including a lower pattern and an upper pattern on a substrate, the upper pattern including a plurality of sacrificial layers and a plurality of sheet patterns alternately stacked on the lower pattern; forming a field insulating film on the substrate and the fin type pattern such that the field insulation film covers side walls of the lower pattern; forming a passivation film on the field insulating film such that the passivation film extends along an upper surface of the field insulating film; and removing the plurality of sacrificial layers after forming the passivation film.

A ferroelectric memory device may include a source, a drain, a channel layer between the source and the drain and connected to the source and the drain, a first gate electrode and a second gate electrode located on the channel layer to be spaced apart from each other, and a ferroelectric layer between the channel layer and the first gate electrode and between the channel layer and the second gate electrode. Different voltages may be applied to the first gate electrode and the second gate electrode.

Provided are a semiconductor device and a semiconductor apparatus including the semiconductor device. The semiconductor device includes a substrate having a channel layer comprising a dopant, a ferroelectric layer on the channel layer; and a gate on the ferroelectric layer. The channel layer has a doping concentration of 1×10.sup.15 cm.sup.−3 to 1×10.sup.21 cm.sup.−3.

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin comprising silicon, the fin having a lower fin portion and an upper fin portion. A first insulating layer is directly on sidewalls of the lower fin portion of the fin, wherein the first insulating layer is a non-doped insulating layer comprising silicon and oxygen. A second insulating layer is directly on the first insulating layer directly on the sidewalls of the lower fin portion of the fin, the second insulating layer comprising silicon and nitrogen. A dielectric fill material is directly laterally adjacent to the second insulating layer directly on the first insulating layer directly on the sidewalls of the lower fin portion of the fin.

In some embodiments, the present disclosure relates to a method for forming an integrated circuit (IC), including forming a first electrode layer having a first metal over a substrate, performing a first atomic layer deposition (ALD) pulse that exposes the first electrode layer to oxygen atoms, exposing the first electrode layer to a first temperature, the first temperature causing the first electrode layer to react with the oxygen atoms to form a seed structure over the first electrode layer, and performing a series of ALD pulses at a second temperature to form a ferroelectric structure over the seed structure. The second temperature is less than the first temperature and the ferroelectric structure is configured to store a data state.

Ferroelectric field effect transistors (FeFETs) having band-engineered interface layers are described. In an example, an integrated circuit structure includes a semiconductor channel layer above a substrate. A metal oxide material is on the semiconductor channel layer, the metal oxide material having no net dipole. A ferroelectric oxide material is on the metal oxide material. A gate electrode is on the ferroelectric oxide material, the gate electrode having a first side and a second side opposite the first side. A first source/drain region is at the first side of the gate electrode, and a second source/drain region is at the second side of the gate electrode.