A ferroelectric memory device according to one embodiment includes a semiconductor substrate, a fin structure disposed on the semiconductor substrate and having a trench, the trench having a bottom surface and a sidewall surface; a ferroelectric layer disposed on the bottom surface and the sidewall surface of the trench; a plurality of resistor layers stacked vertically in the trench, each resistor layer of the plurality of resistor layers having a different electrical resistance; and a gate electrode layer electrically connected to the each resistor layer in the plurality of resistor layers. The plurality of resistor layers are disposed between the gate electrode layer and the ferroelectric layer.

The present disclosure relates to a semiconductor device including a substrate and first and second spacers on the substrate. The semiconductor device also includes a gate stack between the first and second spacers. The gate stack includes a gate dielectric layer having a first portion formed on the substrate and a second portion formed on the first and second spacers; an internal gate formed on the first and second portions of the gate dielectric layer; a ferroelectric dielectric layer formed on the internal gate and in contact with the gate dielectric layer; and a gate electrode on the ferroelectric dielectric layer.

The present disclosure provides a method of forming a semiconductor device including an nFET structure and a pFET structure where each of the nFET and pFET structures include a semiconductor substrate and a gate trench. The method includes depositing an interfacial layer in each gate trench; depositing a first metal oxide layer over the interfacial layer; removing the first metal oxide layer from the pFET structure; depositing a ferroelectric layer in each gate trench; depositing a second metal oxide layer over the ferroelectric layer; removing the second metal oxide layer from the nFET structure; and depositing a gate electrode in each gate trench.

Provided is a semiconductor device which use a two-dimensional semiconductor material as a channel layer. The semiconductor device includes: a gate electrode on a substrate; a gate dielectric on the gate electrode; a channel layer on the gate dielectric; and a source electrode and a drain electrode that may be electrically connected to the channel layer. The gate dielectric has a shape with a height greater than a width, and the channel layer includes a two-dimensional semiconductor material.

According to various aspects, a method of forming one or more remanent-polarizable capacitive structures, the method including forming one or more capacitive structures, each of the one or more capacitive structures includes: one or more electrodes, one or more precursor structures disposed adjacent to the one or more electrodes, wherein each of the one or more precursor structures has a first dimension in a range from about 1 nm to 100 nm and a second dimension in a range from about 1 nm to about 30 nm; and, subsequently, forming one or more remanent-polarizable structures comprising a crystalline remanent-polarizable material based on a crystallization of a precursor material of the one or more precursor structures.

A ferroelectric memory device includes a semiconductor substrate, a fin structure disposed on the semiconductor substrate and having a trench, the trench having a bottom surface and a sidewall surface; a ferroelectric layer disposed on the bottom surface and the sidewall surface of the trench; a plurality of resistor layers stacked vertically in the trench, each resistor layer of the plurality of resistor layers having a different electrical resistance; and a gate electrode layer electrically connected to the each resistor layer in the plurality of resistor layers. The plurality of resistor layers are disposed between the gate electrode layer and the ferroelectric layer.

Semiconductor device and the manufacturing method thereof are disclosed. An exemplary method comprises forming a first stack structure and a second stack structure in a first area over a substrate, wherein each of the stack structures includes semiconductor layers separated and stacked up; depositing a first interfacial layer around each of the semiconductor layers of the stack structures; depositing a gate dielectric layer around the first interfacial layer; forming a dipole oxide layer around the gate dielectric layer; removing the dipole oxide layer around the gate dielectric layer of the second stack structure; performing an annealing process to form a dipole gate dielectric layer for the first stack structure and a non-dipole gate dielectric layer for the second stack structure; and depositing a first gate electrode around the dipole gate dielectric layer of the first stack structure and the non-dipole gate dielectric layer of the second stack structure.

A ferroelectric tunnel junction (FTJ) memory device may include a first electrode and a ferroelectric layer comprising ferroelectric dipoles that may generate a first electric field. The first electric field may be oriented in a first direction when the device operates in an ON state. The device may also include a barrier layer that may generate a depolarizing second electric field that may be oriented in a second direction opposite of the first direction when the device operates in the ON state. The device may further include a second electrode. The first electrode and the second electrode may generate a third electric field that is oriented in the first direction when the device operates in the ON state.

A device includes a multi-layer stack, a channel layer, a ferroelectric layer and buffer layers. The multi-layer stack is disposed on a substrate and includes a plurality of conductive layers and a plurality of dielectric layers stacked alternately. The channel layer penetrates through the plurality of conductive layers and the plurality of dielectric layers. The ferroelectric layer is disposed between the channel layer and each of the plurality of conductive layers and the plurality of dielectric layers. The buffer layers include a metal oxide, and one of the buffer layers is disposed between the ferroelectric layer and each of the plurality of dielectric layers.

Semiconductor devices and methods of forming the same are provided. A semiconductor device according to the present disclosure includes a first gate electrode, a ferroelectric insulating layer over the first gate electrode, a semiconductor member over the ferroelectric insulating layer, a gate dielectric layer over the semiconductor member, and a second gate electrode over the gate dielectric layer.