Methods for forming a semiconductor structure including a gallium nitride dipole layer are disclosed. An exemplary method includes using a cyclical deposition process to deposit a dipole layer comprising gallium nitride over a surface of a gate dielectric. The cyclical deposition process can include providing a gallium precursor to the reaction chamber and separately providing a nitrogen reactant to the reaction chamber. The cyclical deposition process may desirably be a thermal cyclical deposition process. Exemplary structures can include field effect transistor structures, such as gate all around structures.

Two or more types of fin-based transistors having different gate structures and formed on a single integrated circuit are described. The gate structures for each type of transistor are distinguished at least by the thickness or composition of the gate dielectric layer(s) or the composition of the work function metal layer(s) in the gate electrode. Methods are also provided for fabricating an integrated circuit having at least two different types of fin-based transistors, where the transistor types are distinguished by the thickness and composition of the gate dielectric layer(s) and/or the thickness and composition of the work function metal in the gate electrode.

Energy bands of a thin film containing molecular clusters are tuned by controlling the size and the charge of the clusters during thin film deposition. Using atomic layer deposition, an ionic cluster film is formed in the gate region of a nanometer-scale transistor to adjust the threshold voltage, and a neutral cluster film is formed in the source and drain regions to adjust contact resistance. A work function semiconductor material such as a silver bromide or a lanthanum oxide is deposited so as to include clusters of different sizes such as dimers, trimers, and tetramers, formed from isolated monomers. A type of Atomic Layer Deposition system is used to deposit on semiconductor wafers molecular clusters to form thin film junctions having selected energy gaps. A beam of ions contains different ionic clusters which are then selected for deposition by passing the beam through a filter in which different apertures select clusters based on size and orientation.

A semiconductor device is provided and includes a substrate and a stack on the substrate. The stack includes plural active layers that are vertically stacked and spaced apart from each other, and plural gate electrodes that are on the active layers, respectively, and vertically stacked. Each active layer includes a channel layer under a corresponding one of the gate electrodes, and a source/drain layer disposed at a side of the channel layer and electrically connected to the channel layer. The channel layer is made of a two-dimensional atomic layer of a first material.

In a method of forming a FinFET, a first sacrificial layer is formed over a source/drain structure of a FinFET structure and an isolation insulating layer. The first sacrificial layer is recessed so that a remaining layer of the first sacrificial layer is formed on the isolation insulating layer and an upper portion of the source/drain structure is exposed. A second sacrificial layer is formed on the remaining layer and the exposed source/drain structure. The second sacrificial layer and the remaining layer are patterned, thereby forming an opening. A dielectric layer is formed in the opening. After the dielectric layer is formed, the patterned first and second sacrificial layers are removed to form a contact opening over the source/drain structure. A conductive layer is formed in the contact opening.

Methods for forming a semiconductor device structure are provided. The methods may include forming a molybdenum nitride film on a substrate by atomic layer deposition by contacting the substrate with a first vapor phase reactant comprising a molybdenum halide precursor, contacting the substrate with a second vapor phase reactant comprise a nitrogen precursor, and contacting the substrate with a third vapor phase reactant comprising a reducing precursor. The methods provided may also include forming a gate electrode structure comprising the molybdenum nitride film, the gate electrode structure having an effective work function greater than approximately 5.0 eV. Semiconductor device structures including molybdenum nitride films are also provided.

In a silicon carbide semiconductor device and a silicon carbide semiconductor circuit device equipped with the silicon carbide semiconductor device, a gate leak current that flows when negative voltage with respect to the potential of a source electrode is applied to the gate electrode is limited to less than 2×10.sup.−11 A and the gate leak current is limited to less than 3.7×10.sup.−6 A/m.sup.2.

The structure of a semiconductor device with passivation layers on active regions of FET devices and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes a substrate, first and second source/drain (S/D) regions disposed on the substrate, nanostructured channel regions disposed between the first and second S/D regions, a passivation layer, and a nanosheet (NS) structure wrapped around the nanostructured channel regions. Each of the S/D regions have a stack of first and second semiconductor layers arranged in an alternating configuration and an epitaxial region disposed on the stack of first and second semiconductor layers. A first portion of the passivation layer is disposed between the epitaxial region and the stack of first and second semiconductor layers and a second portion of the passivation layer is disposed on sidewalls of the nanostructured channel regions.

A method includes forming a gate stack, which includes a gate dielectric and a metal gate electrode over the gate dielectric. An inter-layer dielectric is formed on opposite sides of the gate stack. The gate stack and the inter-layer dielectric are planarized. The method further includes forming an inhibitor film on the gate stack, with at least a portion of the inter-layer dielectric exposed, selectively depositing a dielectric hard mask on the inter-layer dielectric, with the inhibitor film preventing the dielectric hard mask from being formed thereon, and etching to remove a portion of the gate stack, with the dielectric hard mask acting as a portion of a corresponding etching mask.

A semiconductor device with high reliability is provided. The semiconductor device includes a first insulator, a second insulator, and a transistor; the transistor includes an oxide in a channel formation region; the oxide is surrounded by the first insulator; and the first insulator is surrounded by the second insulator. The first insulator includes a region with a lower hydrogen concentration than the second insulator. Alternatively, the first insulator includes a region with a lower hydrogen concentration than the second insulator and with a lower nitrogen concentration than the second insulator.