A multilayer composite structure and a method of preparing a multilayer composite structure are provided. The multilayer composite structure comprises a semiconductor handle substrate having a minimum bulk region resistivity of at least about 500 ohm-cm; a silicon dioxide layer on the surface of the semiconductor handle substrate; a carbon-doped amorphous silicon layer in contact with the silicon dioxide layer; a dielectric layer in contact with the carbon-doped amorphous silicon layer; and a semiconductor device layer in contact with the dielectric layer.

A tunnel field-effect transistor and method fabricating the same are provided. The tunnel field-effect transistor includes a drain region, a source region with opposite conductive type to the drain region, a channel region disposed between the drain region and the source region, a metal gate layer disposed around the channel region, and a high-k dielectric layer disposed between the metal gate layer and the channel region.

A semiconductor device includes a semiconductor layer, a first electrode located over the semiconductor layer and connected to the semiconductor layer, a second electrode spaced from the first electrode and located over the semiconductor layer and connected to the semiconductor layer, an insulation film located over the semiconductor layer, and a third electrode interposed between the first electrode and the second electrode, and location over a portion of the insulation film. The insulation film includes a first layer located on the semiconductor layer and between the first electrode and the second electrode and comprising silicon nitride, and a second layer located on the first layer and between the first electrode and the third electrode as well as between the second electrode and the third electrode, and comprising silicon nitride and an amount of oxygen larger than the first layer.

A method for reducing parasitic capacitance of a semiconductor structure is provided. The method includes forming a fin structure over a substrate, forming a first source/drain region between the fin structure and the substrate, forming first spacers adjacent the fin structure, forming second spacers adjacent the first source/drain region and recessing the first source/drain region in exposed areas. The method further includes forming a shallow trench isolation (STI) region within the exposed areas of the recessed first source/drain region, depositing a bottom spacer over the STI region, forming a metal gate stack over the bottom spacer, depositing a top spacer over the metal gate stack, cutting the metal gate stack, forming a second source/drain region over the fin structure, and forming contacts such the STI region extends a length between the metal gate stack and the first source/drain region.

A semiconductor device according to an embodiment, includes: a silicon carbide layer; a gate electrode; and a gate insulating layer, the gate electrode including a p-type silicon carbide region containing aluminum, the gate insulating layer having a first region and a second region, the first region including a silicon oxide or a silicon oxynitride, the second region being positioned between the first region and the gate electrode, the second region including an oxide containing aluminum.

An object of the present invention is to apply an insulating film of cure and high quality that is suitably applicable as gate insulating film and protective film to a technique that the insulating film is formed on the glass substrate under a temperature of strain point or lower, and to a semiconductor device realizing high efficiency and high reliability by using it. In a semiconductor device of the present invention, a gate insulating film of a field effect type transistor with channel length of from 0.35 to 2.5 μm in which a silicon nitride film is formed over a crystalline semiconductor film through a silicon oxide film, wherein the silicon nitride film contains hydrogen with the concentration of 1×10.sup.21/cm.sup.3 or less and has characteristic of an etching rate of 10 nm/min or less with respect to mixed solution containing an ammonium hydrogen fluoride (NH.sub.4HF.sub.2) of 7.13% and an ammonium fluoride (NH.sub.4F) of 15.4%.

Techniques are disclosed for providing an integrated circuit structure having NMOS transistors including an arsenic-doped interface layer between epitaxially grown source/drain regions and a channel region. The arsenic-doped interface layer may include, for example, arsenic-doped silicon (Si:As) having arsenic concentrations in a range of about 1E20 atoms per cm.sup.3 to about 5E21 atoms per cm.sup.3. The interface layer may have a relatively uniform thickness in a range of about 0.5 nm to full fill where the entire source/drain region is composed of the Si:As. In cases where the arsenic-doped interface layer only partially fills the source/drain regions, another n-type doped semiconductor material can fill remainder (e.g., phosphorus-doped III-V compound or silicon). The use of a layer having a high arsenic concentration can provide improved NMOS performance in the form of abrupt junctions in the source/drain regions and highly conductive source/drain regions with negligible diffusion of arsenic into the channel region.

A method for fabricating a Fin-FET includes forming a plurality of fin structures, an isolation layer, and an interlayer dielectric layer on an NMOS region of a substrate, forming a first opening in the interlayer dielectric layer to expose a portion of the fin structures. A region adjacent to a joint between a bottom surface and a sidewall surface of the first opening is a corner region. The method includes forming a high-k dielectric layer on the bottom and the sidewall surfaces of the first opening, a barrier layer on the high-k dielectric layer, and an N-type work function layer containing aluminum ions on the barrier layer. The method further includes performing a back-flow annealing process such that the portion of N-type work function layer at the corner region is thickened and contains diffused aluminum ions. Finally, the method includes forming a metal layer on the N-type work function layer.

The present application provides a memory device having several word lines (WL) with reduced leakage and a manufacturing method of the memory device. The memory device includes a semiconductor substrate defined with an active area and including a recess extending into the semiconductor substrate; and a word line disposed within the recess, wherein the word line includes an insulating layer disposed within the recess, a conductive layer surrounded by the insulating layer, and a conductive member enclosed by the conductive layer, and the insulating layer includes a lining portion conformal to the recess and a protruding portion disposed above the conductive layer. A method of manufacturing the memory device is also disclosed.

A processing method of a silicon nitride film can modify a silicon nitride film such that the silicon nitride film has a required characteristic even if it is formed at a low temperature by CVD. The processing method of the silicon nitride film formed on a substrate by plasma CVD includes modifying a surface portion of the silicon nitride film by irradiating microwave hydrogen plasma to the silicon nitride film to remove hydrogens in the surface portion of the silicon nitride film with atomic hydrogens contained in the microwave hydrogen plasma.