In an embodiment, a semiconductor device includes a first channel region disposed in a first device region over a substrate; a first gate dielectric layer disposed over the first channel region; and a gate electrode disposed over the first gate dielectric layer. The first gate dielectric layer includes a first dipole dopant and a second dipole dopant. The first dipole dopant along a thickness direction of the first gate dielectric layer has a first concentration peak, and the second dipole dopant along the thickness direction of the first gate dielectric layer has a second concentration peak. The second concentration peak is located between the first concentration peak and an upper surface of the first gate dielectric layer. The second concentration peak is offset from the upper surface of the first gate dielectric layer.

In a semiconductor device, a gate insulating film is provided with a multi-layer structure including a first insulating film and a second insulating film. The first insulating film is formed of an insulating film containing an element having an oxygen binding force larger than that of an element contained in the second insulating film, and the total charge amount is increased. Specifically, by performing oxygen anneal, it is possible to perform the step of supplying oxygen into an aluminum oxide film and increase the total charge amount. This allows a negative fixed charge density in the gate insulating film in the vicinity of an interface with a GaN layer to be set to a value of not less than 2.5×10.sup.11 cm.sup.−2 and allows a normally-off element to be reliably provided.

A semiconductor device of the present invention includes a semiconductor layer of a first conductivity type having a cell portion and an outer peripheral portion disposed around the cell portion, formed with a gate trench at a surface side of the cell portion, and a gate electrode buried in the gate trench via a gate insulating film, forming a channel at a portion lateral to the gate trench at ON-time, the outer peripheral portion has a semiconductor surface disposed at a depth position equal to or deeper than a depth of the gate trench, and the semiconductor device further includes a voltage resistant structure having a semiconductor region of a second conductivity type formed in the semiconductor surface of the outer peripheral portion.

The present disclosure provides a semiconductor structure. The semiconductor structure comprises a semiconductor substrate comprising two source/drain regions, a gate stack over the semiconductor substrate and between the source/drain regions, and a spacer over the semiconductor substrate and surrounding the gate stack. The spacer comprises a carbon-containing layer and a carbon-free layer.

An n-type metal-oxide-semiconductor (NMOS) transistor comprises a graphene channel with a chemically adsorbed nitrogen dioxide (NO.sub.2) layer formed thereon. The NMOS transistor may comprise a substrate having a graphene layer formed thereon and a gate stack formed on a portion of the graphene layer disposed in a channel region that further includes a spacer region. The gate stack may comprise the chemically adsorbed NO.sub.2 layer formed on the graphene channel, a high-k dielectric formed over the adsorbed NO.sub.2 layer, a gate metal formed over the high-k dielectric, and spacer structures formed in the spacer region. The adsorbed NO.sub.2 layer formed under the gate and the spacer structures may therefore attract electrons from the graphene channel to turn the graphene-based NMOS transistor off at a gate voltage (V.sub.g) equal to zero, making the graphene-based NMOS transistor suitable for digital logic applications.

To provide a method by which a semiconductor device including a thin film transistor with excellent electric characteristics and high reliability is manufactured with a small number of steps. After a channel protective layer is formed over an oxide semiconductor film containing In, Ga, and Zn, a film having n-type conductivity and a conductive film are formed, and a resist mask is formed over the conductive film. The conductive film, the film having n-type conductivity, and the oxide semiconductor film containing In, Ga, and Zn are etched using the channel protective layer and gate insulating films as etching stoppers with the resist mask, so that source and drain electrode layers, a buffer layer, and a semiconductor layer are formed.

A semiconductor device is provided with, a group-III nitride semiconductor layered structure that includes a heterojunction, an insulating layer which has a gate opening that reaches the group-III nitride semiconductor layered structure and which is disposed on the group-III nitride semiconductor layered structure, a gate insulating film that covers the bottom and the side of the gate opening, a gate electrode defined on the gate insulating film inside the gate opening, a source electrode and a drain electrode which are disposed to be spaced apart from the gate electrode so as to sandwich the gate electrode, a first conductive layer embedded in the insulating layer between the gate electrode and the drain electrode, and a second conductive layer that is embedded in the insulating layer above the first conductive layer in a region closer to the drain electrode side than the first conductive layer.

A method of controlling the thickness of gate oxides in an integrated CMOS process which includes performing a two-step gate oxidation process to concurrently oxidize and therefore consume at least a first portion of the cap layer of the NV gate stack to form a blocking oxide and form a gate oxide of at least one metal-oxide-semiconductor (MOS) transistor in the second region, wherein the gate oxide of the at least one MOS transistor is formed during both a first oxidation step and a second oxidation step of the gate oxidation process.

The present invention provides a MIS-type semiconductor device having a ZrO.sub.xN.sub.y gate insulating film in which threshold voltage shift is suppressed, thereby achieving stable operation. In the MIS-type semiconductor device having a gate insulating film on the semiconductor layer and a gate electrode on the gate insulating film, with a gate applied voltage of 5 V or more, the gate insulating film is formed of ZrO.sub.xN.sub.y (x and y satisfy the relation: x>0, y>0, 0.8≦y/x≦10, and 0.8≦0.59x+y≦1.0). The MIS-type semiconductor device having such a gate insulating film can perform stable operation because there is no shift in the threshold voltage even if a high voltage is applied to the gate electrode.

The present disclosure describes a semiconductor structure that includes a substrate from an undoped semiconductor material and a fin disposed on the substrate. The fin includes a non-polar top surface and two opposing first and second polar sidewall surfaces. The semiconductor structure further includes a polarization layer on the first polar sidewall surface, a doped semiconductor layer on the polarization layer, a dielectric layer on the doped semiconductor layer and on the second polar sidewall surface, and a gate electrode layer on the dielectric layer and the first polarized sidewall surface.