Charge storage and sensing devices having a tunnel diode operable to sense charges stored in a charge storage structure are provided. In some embodiments, a device includes a substrate, a charge storage device on the substrate, and tunnel diode on the substrate adjacent to the charge storage device. The tunnel diode includes a tunnel diode dielectric layer on the substrate, and a tunnel diode electrode on the tunnel diode dielectric layer. A substrate electrode is disposed on the doped region of the substrate, and the tunnel diode electrode is positioned between the charge storage device and the substrate electrode.

Semiconductor device having less defects in a gate insulating film and improved reliability and methods of forming the semiconductor devices are provided. The semiconductor devices may include a gate insulating film on a substrate and a gate electrode structure on the gate insulating film. The gate electrode structure may include a lower conductive film, a silicon oxide film, and an upper conductive film sequentially stacked on the gate insulating film. The lower conductive film may include a barrier metal layer.

A semiconductor device includes a compound semiconductor layer comprising a III-V material; a first layer on the compound semiconductor layer and comprising oxygen, nitrogen, and a material included in the compound semiconductor layer; a second layer over the first layer, wherein at least a portion of the second layer comprises a single crystalline structure or a polycrystalline structure; a dielectric layer over the second layer; and a source/drain electrode extending through the dielectric layer, the second layer, and the first layer and into the compound semiconductor layer.

Disclosed is a fin field-effect transistor having size-reduced source/drain regions so that a merging phenomenon of epitaxial structures between transistors in a layout is prevented, thus increasing the number of transistors per unit area, and so that an additional mask process is not required, thus maintain processing costs without change, and a method of manufacturing the same.

Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device includes a gate electrode separated from a substrate by a gate dielectric. The gate electrode has one or more interior surfaces that form a recess within the gate electrode. A dielectric layer is disposed over the substrate and laterally surrounds the gate electrode. A dishing prevention structure is disposed within the recess. The dishing prevention structure is both vertically separated from the gate dielectric and laterally separated from the dielectric layer by the gate electrode. The dishing prevention structure continuously extends between outermost sidewalls of the dishing prevention structure as viewed along a cross-sectional view extending through a center of the recess.

A non-volatile memory (NVM) cell includes a semiconductor wire including a select gate portion and a control gate portion. The NVM cell includes a select transistor formed with the select gate portion and a control transistor formed with the control gate portion. The select transistor includes a gate dielectric layer disposed around the select gate portion and a select gate electrode disposed on the gate dielectric layer. The control transistor includes a stacked dielectric layer disposed around the control gate portion, a gate dielectric layer disposed on the stacked dielectric layer and a control gate electrode disposed on the gate dielectric layer. The stacked dielectric layer includes a first silicon oxide layer disposed on the control gate portion, a charge trapping layer disposed on the first silicon oxide, and a second silicon oxide layer disposed on the charge trapping layer.

Metal gate stacks and integrated methods of forming metal gate stacks are disclosed. Some embodiments comprise NbN as a PMOS work function material at a thickness in a range of greater than or equal to 5 Å to less than or equal to 50 Å. The PMOS work function material comprising NbN has an effective work function of greater than or equal to 4.75 eV. Some embodiments comprise HfO.sub.2 as a high-κ metal oxide layer. Some embodiments provide improved PMOS bandedge performance evidenced by improved flatband voltage. Some embodiments exclude transition metal niobium nitride materials as work function materials.

The present application discloses a method for fabricating a semiconductor device includes providing a substrate, forming a gate stack on the substrate and a pair of heavily-doped regions in the substrate, forming a programmable contact having a first width on the gate stack, and forming a first contact having a second width, which is greater than the first width, on one of the pair of heavily-doped regions.

A semiconductor device includes: a first electrode; a first semiconductor layer of first conductivity type provided on the first electrode; a second semiconductor layer of first conductivity type provided on the first semiconductor layer; a first semiconductor region of second conductivity type provided on the second semiconductor layer; a second semiconductor region of second conductivity type provided on the second semiconductor layer; a first insulating film provided in a trench between the first semiconductor region and the second semiconductor region, the trench reaching the second semiconductor layer from above the first semiconductor region and the second semiconductor region, the first insulating film containing silicon oxide; a second electrode provided in the trench, the second electrode facing the second semiconductor layer via the first insulating film, the second electrode containing polysilicon; a third electrode provided above the second electrode, the third electrode facing the first semiconductor region and the second semiconductor region via a second insulating film containing silicon oxide; a third insulating film provided between the second electrode and the third electrode, the third insulating film containing silicon nitride; a third semiconductor region of first conductivity type provided on the first semiconductor region; a fourth semiconductor region of first conductivity type provided on the second semiconductor region; an interlayer insulating film provided on the third electrode; and a fourth electrode provided on the interlayer insulating film, the fourth electrode being electrically connected to the third semiconductor region and the fourth semiconductor region.

A semiconductor device and method of manufacturing are provided. In an embodiment a first nucleation layer is formed within an opening for a gate-last process. The first nucleation layer is treated in order to remove undesired oxygen by exposing the first nucleation layer to a precursor that reacts with the oxygen to form a gas. A second nucleation layer is then formed, and a remainder of the opening is filled with a bulk conductive material.