A semiconductor device includes: a substrate including first and second regions thereon; a first active region in the first region; an active pattern protruding from the first active region; a second active region in the second region; a first gate electrode on the active pattern; a second gate electrode on the second active region; a first gate insulating layer, including a first-first insulating layer, between the active pattern and the first gate electrode; and a second gate insulating layer, including a second-first insulating layer and a second-second insulating layer below the second-first insulating layer, between the second active region and the second gate electrode, wherein a thickness in a vertical direction of the first gate electrode that overlaps the active pattern in the vertical direction is equal to a thickness in the vertical direction of the second gate electrode that overlaps the second active region in the vertical direction, and an upper surface of the first gate electrode is formed at a same level as an upper surface of the second gate electrode.

A semiconductor device includes a substrate and a gate structure. The gate structure is disposed on the substrate, and the gate structure includes a titanium nitride barrier layer a titanium aluminide layer, and a middle layer. The titanium aluminide layer is disposed on the titanium nitride barrier layer, and the middle layer is disposed between the titanium aluminide layer and the titanium nitride barrier layer. The middle layer is directly connected with the titanium aluminide layer and the titanium nitride barrier layer, and the middle layer includes titanium and nitrogen. A concentration of nitrogen in the middle layer is gradually decreased in a vertical direction towards an interface between the middle layer and the titanium aluminide layer.

A semiconductor device of embodiments includes: a silicon carbide layer having a first face having an off angle equal to or more than 0° and equal to or less than 8° with respect to a {0001} face and a second face facing the first face and having a 4H-SiC crystal structure; a gate electrode extending in a first direction parallel to the first face; a silicon oxide layer between the silicon carbide layer and the gate electrode; and a region disposed between the silicon carbide layer and the silicon oxide layer and having a nitrogen concentration equal to or more than 1 × 10.sup.21 cm.sup.-3. Assuming that a first reference length in the first direction is 0.5 .Math.m, a surface roughness of a surface of the silicon carbide layer in a range of the first reference length is equal to or less than 1 nm.

Examples of an integrated circuit with a gate structure and a method for forming the integrated circuit are provided herein. In some examples, a workpiece is received that includes a substrate having a channel region. A gate dielectric is formed on the channel region, and a layer containing a dopant is formed on the gate dielectric. The workpiece is annealed to transfer the dopant to the gate dielectric, and the layer is removed after the annealing. In some such examples, after the layer is removed, a work function layer is formed on the gate dielectric and a fill material is formed on the work function layer to form a gate structure.

The present disclosure relates to a semiconductor device including a substrate having a top surface and a gate stack. The gate stack includes a gate dielectric layer on the substrate and a gate electrode on the gate dielectric layer. The semiconductor device also includes a multi-spacer structure. The multi-spacer includes a first spacer formed on a sidewall of the gate stack, a second spacer, and a third spacer. The second spacer includes a first portion formed on a sidewall of the first spacer and a second portion formed on the top surface of the substrate. The second portion of the second spacer has a thickness in a first direction that gradually decreases. The third spacer is formed on the second portion of the second spacer and on the top surface of the substrate. The semiconductor device further includes a source/drain region formed in the substrate, and a portion of the third spacer abuts the source/drain region and the second portion of the second spacer.

A semiconductor device includes a semiconductor substrate having a main surface, a gate electrode formed on the main surface of the semiconductor substrate, a side-wall oxide film formed on a side wall of the gate electrode, a first insulating layer formed on the gate electrode and containing silicon nitride, and a second insulating layer formed between the gate electrode and the first insulating layer and containing silicon oxide.

A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.

A semiconductor device includes a PMOS region and a NMOS region on a substrate, a first fin-shaped structure on the PMOS region, a first single diffusion break (SDB) structure in the first fin-shaped structure, a first gate structure on the first SDB structure, and a second gate structure on the first fin-shaped structure. Preferably, the first gate structure and the second gate structure are of different materials and the first gate structure disposed directly on top of the first SDB structure is a polysilicon gate while the second gate structure disposed on the first fin-shaped structure is a metal gate in the PMOS region.

Provided are a memory device and a method of forming the same. The memory device includes a substrate, a layer stack, and a plurality of composite pillar structures. The layer stack is disposed on the substrate. The layer stack includes a plurality of conductive layers and a plurality of dielectric layers stacked alternately. The composite pillar structures respectively penetrate through the layer stack. Each composite pillar structure includes a dielectric pillar; a pair of conductive pillars penetrating through the dielectric pillar and electrically isolated from each other through a portion of the dielectric pillar; a channel layer covering both sides of the dielectric pillar and the pair of conductive pillars; a ferroelectric layer disposed between the channel layer and the layer stack; and a buffer layer disposed between the channel layer and the ferroelectric layer.

Embodiments of the disclosure provide a floating gate memory cell, including: a silicon-on-insulator (SOI) substrate, the SOI substrate including a semiconductor bulk substrate, a buried oxide layer formed on the semiconductor bulk substrate, and a semiconductor layer formed on the buried oxide layer; a memory device, including: a control gate formed in the semiconductor layer of the SOI substrate; an insulating layer formed on the control gate; and a floating gate formed on the insulating layer; and a transistor device electrically connected to the memory device. The transistor device includes an active region formed in the semiconductor layer of the SOI substrate.