A method for manufacturing a fin-type diode includes providing a substrate structure including a substrate, first and second sets of fins on the substrate, an isolation region between the first and second sets of fins and having an upper surface lower than an upper surface of the first and second set of fins, a well region partially in the substrate and overlapping the first and second sets of fins. The method also includes forming a dielectric layer on the first and second sets of fins, forming a dummy gate structure covering the dielectric layer on an end of the second set of fins and the upper surface of the isolation region, doping the first set of fins to form a first doped region, and doping the second set of fins and a portion of the well region below the second set of fins to form a second doped region.

A method of manufacturing a diode structure includes forming a first stack on a silicon layer on a substrate. A first sidewall spacer extending along and covering a sidewall of the first stack is formed. The silicon layer is selectively etched to a first predetermined depth, thereby forming a second stack. The remaining silicon layer includes a silicon base. A second sidewall spacer extending along and covering a sidewall of the second stack is formed. The silicon base is selectively etched to form a third stack on the substrate. With the second sidewall spacer as a mask, lateral plasma ion implantation is performed. Defects at the interface between two adjacent semiconductor layers can be reduced by the method.

Vertical etch heterolithic integrated circuit devices are described. A method of manufacturing NIP diodes is described in one example. A P-type substrate is provided, and an intrinsic layer is formed on the P-type substrate. An oxide layer is formed on the intrinsic layer, and one or more openings are formed in the oxide layer. One or more N-type regions are implanted in the intrinsic layer through the openings in the oxide layer. The N-type regions form cathodes of the NIP diodes. A dielectric layer deposited over the oxide layer is selectively etched away with the oxide layer to expose certain ranges of the intrinsic layer to define a geometry of the NIP diodes. The intrinsic layer and the P-type substrate are vertically etched away within the ranges to expose sidewalls of the intrinsic layer and the P-type substrate. The P-type substrate forms the anodes of the NIP diodes.

A method is presented for integrating an electronic component in back end of the line (BEOL) processing. The method includes forming a first electrode over a semiconductor substrate, forming a first electrically conductive material over a portion of the first electrode, and forming a second electrically conductive material over the first electrically conductive material, where the first and second electrically conductive materials define a p-n junction. The method further includes depositing a second electrode between a set of spacers and in direct contact with the p-n-junction, depositing a phase change material over the p-n junction and in direct contact with the second electrode, and forming a third electrode over a portion of the phase change material.

A semiconductor element capable of adjusting a barrier height .sub.Bn and performing zero-bias operation and impedance matching with an antenna for improving detection sensitivity of high-frequency RF electric signals, a method of manufacturing the same, and a semiconductor device having the same. In the semiconductor element, a concentration of InGaAs (n-type InGaAs layer) is intentionally set to be high over a range for preventing the change of the barrier height caused by the bias described above up to a deep degeneration range. An electron Fermi level (E.sub.F) increases from a band edge of InGaAs (n-type InGaAs layer) to a band edge of InP (InP depletion layer).

A preparation method for a GaAs/Ge/GaAs heterogeneous SPiN diode for a loop antenna includes: selecting a GeOI substrate; etching a top Ge layer of the GeOI substrate to form first and second trenches in the top Ge layer; depositing a GaAs material in, the first and second trenches; performing P-type ion implantation into the GaAs material in the first trench to form a P-type active region and performing an N-type ion implantation into the GaAs material in the second trench to form an N-type active region by ion implantation process; and forming lead holes on surfaces of the P-type active region and the N-type active region and then sputtering a metal to form the GaAs/Ge/GaAs heterogeneous SPiN diode. Therefore, a high performance GaAs/Ge/GaAs heterogeneous SPiN diode suitable for forming a solid-state plasma antenna can be prepared by deep trench isolation technology and ion implantation process.

Disclosed is an integrated circuit (IC) structure that incorporates a string of vertical devices. Embodiments of the IC structure include a string of two or more vertical diodes. Other embodiments include a vertical diode/silicon-controlled rectifier (SCR) string and, more particularly, a diode-triggered silicon-controlled rectifier (VDTSCR). In any case, each embodiment of the IC structure includes an N-well in a substrate and, within that N-well, a P-doped region and an N-doped region that abuts the P-doped region. The P-doped region can be anode of a vertical diode and can be electrically connected to the N-doped region (e.g., by a local interconnect or by contacts and metal wiring) such that the vertical diode is electrically connected to another vertical device (e.g., another vertical diode or a SCR with vertically-oriented features). Also disclosed is a manufacturing method that can be integrated with methods of manufacturing vertical field effect transistors (VFETs).

Disclosed is an integrated circuit (IC) structure that incorporates a string of vertical devices. Embodiments of the IC structure include a string of two or more vertical diodes. Other embodiments include a vertical diode/silicon-controlled rectifier (SCR) string and, more particularly, a diode-triggered silicon-controlled rectifier (VDTSCR). In any case, each embodiment of the IC structure includes an N-well in a substrate and, within that N-well, a P-doped region and an N-doped region that abuts the P-doped region. The P-doped region can be anode of a vertical diode and can be electrically connected to the N-doped region (e.g., by a local interconnect or by contacts and metal wiring) such that the vertical diode is electrically connected to another vertical device (e.g., another vertical diode or a SCR with vertically-oriented features). Also disclosed is a manufacturing method that can be integrated with methods of manufacturing vertical field effect transistors (VFETs).

A method of fabricating an electronic device includes providing a III-V substrate having a hexagonal crystal structure and a normal to a growth surface characterized by a misorientation from the <0001> direction of between 0.15? and 0.65?. The method also includes growing a first III-V epitaxial layer coupled to the III-V substrate and growing a second III-V epitaxial layer coupled to the first III-V epitaxial layer. The method further includes forming a first contact in electrical contact with the III-V substrate and forming a second contact in electrical contact with the second III-V epitaxial layer.

A silicon oxide film having at least one opening portion is formed, on a silicon substrate. A structural member formed of a material less prone to be etched by hydrofluoric acid than a silicon oxide film is formed, wherein the structural member is provided on the silicon oxide film and reaches the silicon substrate in the opening portion. Wet etching using hydrofluoric acid is performed, on the silicon substrate on which the silicon oxide film and the structural member are provided. The interface between the silicon oxide film and the structural member is exposed to hydrofluoric acid, in performing the wet etching.