A semiconductor device and a process of forming the semiconductor device are disclosed. The semiconductor device type of a high electron mobility transistor (HEMT) has double SiN films on a semiconductor layer, where the first SiN film is formed by the lower pressure chemical vapor deposition (LPCVD) technique, while, the second SiN film is deposited by the plasma assisted CVD (p-CVD) technique. Moreover, the gate electrode has an arrangement of double metals, one of which contains nickel (Ni) as a Schottky metal, while the other is free from Ni and covers the former metal. A feature of the invention is that the first metal is in contact with the semiconductor layer but apart from the second SiN film.

A nitride semiconductor device includes a substrate; a nitride semiconductor layered structure disposed on the substrate and having a channel region; a first electrode and a second electrode both disposed on the nitride semiconductor layered structure; a first p-type nitride semiconductor layer disposed between the first electrode and the second electrode; and a first gate electrode disposed on the first p-type nitride semiconductor layer. The nitride semiconductor layered structure includes a first recess. The first p-type nitride semiconductor layer is at least partially disposed inside the first recess, and is separated from a side surface of the first recess.

A semiconductor device according to an embodiment includes a normally-off transistor having a first source, a first drain, and a first gate; a normally-on transistor having a second source electrically connected to the first drain, a second drain, and a second gate, a capacitor having a first end and a second end, the second end being electrically connected to the second gate, a first diode having a first anode electrically connected between the second end and the second gate and having a first cathode electrically connected to the second source, a first resistor provided between the first end and the first gate, and a second diode having a second anode electrically connected to the first end and having a second cathode electrically connected to the first gate, the second diode being provided in parallel with the first resistor.

Photonic devices having a quantum well structure that includes a Group III-N material, and a Al.sub.1-xSc.sub.xN cladding layer disposed on the quantum well structure, where 0<x≤0.45, the Al.sub.1-xSc.sub.xN cladding layer having a lower refractive index than the index of refraction of the quantum well structure.

Photonic devices having a quantum well structure that includes a Group III-N material, and a Al.sub.1-xSc.sub.xN cladding layer disposed on the quantum well structure, where 0<x≤0.45, the Al.sub.1-xSc.sub.xN cladding layer having a lower refractive index than the index of refraction of the quantum well structure.

A GaN-on-Si device structure and a method of fabrication are disclosed for improved die yield and device reliability of high current/high voltage lateral GaN transistors. A plurality of conventional GaN device structures comprising GaN epi-layers are fabricated on a silicon substrate (GaN-on-Si die). After processing of on-chip interconnect layers, a trench structure is defined around each die, through the GaN epi-layers and into the silicon substrate. A trench cladding is provided on proximal sidewalls, comprising at least one of a passivation layer and a conductive metal layer. The trench cladding extends over exposed surfaces of the GaN epi-layers, over the interface region with the substrate, and over the exposed surfaces of the interconnect layers. This structure reduces risk of propagation of dicing damage and defects or cracks in the GaN epi-layers into active device regions. A metal trench cladding acts as a barrier for electro-migration of mobile ions.

Disclosed are semiconductor devices including a double gate metal oxide semiconductor (MOS) transistor and methods for fabricating the same. The double gate MOS transistor includes a first back gate, a second back gate, and a first dielectric layer disposed on the first back gate and on the second back gate. An MX2 material layer is disposed on the first dielectric layer, a second dielectric layer disposed on the MX2 material layer, and a work function metal (WFM) is disposed on the second dielectric layer. A front gate is disposed on the WFM, which fills a space between the first back gate and the second back.

A High Electron Mobility Transistor (HEMT) device can include an AlN buffer layer on a substrate and an epi-GaN channel layer on the AlN buffer layer. An AlN barrier layer can be on the Epi-GaN channel layer to provide a channel region in the epi-GaN channel layer. A GaN drain region can be recessed into the epi-GaN channel layer at a first end of the channel region and a GaN source region can be recessed into the epi-GaN channel layer at a second end of the channel region opposite the first end of the channel region. A gate electrode can include a neck portion with a first width that extends a first distance above the AlN barrier layer between the GaN drain region and the GaN source region to a head portion of the gate electrode having a second width that is greater than the first width.

The semiconductor device includes a semiconductor element, a first lead, and a second lead. The semiconductor element has an element obverse surface and an element reverse surface spaced apart from each other in a thickness direction. The semiconductor element includes an electron transit layer disposed between the element obverse surface and the element reverse surface and formed of a nitride semiconductor, a first electrode disposed on the element obverse surface, and a second electrode disposed on the element reverse surface and electrically connected to the first electrode. The semiconductor element is mounted on the first lead, and the second electrode is joined to the first lead. The second lead is electrically connected to the first electrode. The semiconductor element is a transistor. The second lead is spaced apart from the first lead and is configured such that a main current to be subjected to switching flows therethrough.

A semiconductor structure and a manufacturing method thereof are provided in the present disclosure. The semiconductor structure includes a semiconductor substrate; a plurality of stacked structures and a plurality of isolation structures on the semiconductor substrate, wherein the stacked structures are spaced apart each other, and each of the isolation structures are located between adjacent stacked structures; each of the stacked structures comprises a nucleation layer and a first epitaxial layer from bottom to top; and a heterojunction structure on the plurality of stacked structures, wherein the heterojunction structure is distributed over an entire surface, and an air gap is formed between the heterojunction structure and each of the isolation structures.