Exemplary power semiconductor devices with features providing increased breakdown voltage and other benefits are disclosed.

An integrated diode (100) comprising a substrate (102); a Schottky cell (104) on the substrate (102); a heterojunction cell (106) on the substrate (102); a common anode contact (108) for both the Schottky cell (104) and the heterojunction cell (106); and a common cathode contact (110) for both the Schottky cell (104) and the heterojunction cell (106).

The semiconductor device of the present invention includes a first conductivity type semiconductor layer made of a wide bandgap semiconductor and a Schottky electrode formed to come into contact with a surface of the semiconductor layer, and has a threshold voltage V.sub.th of 0.3 V to 0.7 V and a leakage current J.sub.r of 1×10.sup.−9 A/cm.sup.2 to 1×10.sup.−4 A/cm.sup.2 in a rated voltage V.sub.R.

Apparatus and other embodiments associated with high speed and high breakdown voltage MOS rectifier are disclosed. A Junction All Around structure, where a deep trench structure surrounds and encloses a P-N junction or a MOS structure, is created and applied in various rectifiers. In one embodiment, multiple deep trenches in concentric ring circles enclosed several horizontal P-N junctions in concentric ring circles. In another embodiment, an enclosed deep trench in ring circle surrounds a horizontal P-N junction, which results in a planar N-channel MOS during forward bias. This structure can be extended to multiple deep trenches with associated horizontal P-N junctions.

A trench MOS Schottky diode includes a first semiconductor layer including a Ga.sub.2O.sub.3-based single crystal, a second semiconductor layer that is a layer stacked on the first semiconductor layer, includes a Ga.sub.2O.sub.3-based single crystal, and includes a trench opened on a surface thereof opposite to the first semiconductor layer, an anode electrode formed on the surface of the second semiconductor layer, a cathode electrode formed on a surface of the first semiconductor layer, an insulating film covering the inner surface of the trench of the second semiconductor layer, and a trench electrode that is buried in the trench of the second semiconductor layer so as to be covered with the insulating film and is in contact with the anode electrode. The second semiconductor layer includes an insulating dry-etching-damaged layer with a thickness of not more than 0.8 μm in a region including the inner surface of the trench.

In one embodiment, a breakdown voltage blocking device can include an epitaxial region located above a substrate and a plurality of source trenches formed in the epitaxial region. Each source trench can include a dielectric layer surrounding a conductive region. The breakdown voltage blocking device can also include a contact region located in an upper surface of the epitaxial region along with a gate trench formed in the epitaxial region. The gate trench can include a dielectric layer that lines the sidewalls and bottom of the gate trench and a conductive region located between the dielectric layer. The breakdown voltage blocking device can include source metal located above the plurality of source trenches and the contact region. The breakdown voltage blocking device can include gate metal located above the gate trench.

Described herein are the design and fabrication of Group III trioxides, such as β-Ga.sub.2O.sub.3, trench-MOS barrier Schottky (TMBS) structures with high voltage (>1 kV), low leakage capabilities, while addressing on the necessary methods to meet the re-quirements unique to Group III trioxides, such as β-Ga.sub.2O.sub.3.

A Schottky diode with multiple guard ring structures includes a semiconductor base layer, a back metal layer, an epitaxial layer, a dielectric layer, a first metal layer, a passivation layer and a second metal layer. The epitaxial layer on the semiconductor base layer includes a terminal trench structure, a first ion implantation guard ring, a second ion implantation guard ring and a third ion implantation guard ring. The dielectric layer is on the epitaxial layer in a termination area. The first metal layer is on the terminal trench structure and the dielectric layer. The passivation layer is on the first metal layer and the dielectric layer. The second metal layer is on the first metal layer and the passivation layer. Widths of the first, second and third ion implantation guard rings decrease in order, so that the voltage can be distributed step by step.

A multi-trench schottky diode includes a semiconductor base layer, a back metal layer, an epitaxial layer, an interlayer dielectric layer, a first metal layer, a passivation layer and a second metal layer. The epitaxial layer on the semiconductor base layer includes a termination trench structure, a first trench structure, a second trench structure and a third trench structure. The dielectric layer is on the epitaxial layer in a termination area. The first metal layer stacked on the termination trench structure and the interlayer dielectric layer extends between the second trench structure and the third trench structure. The passivation layer is on the first metal layer and the interlayer dielectric layer. The second metal layer on the first metal layer and the passivation layer extends to the first trench structure. Thus, the electric field is dispersed and the voltage breakdown can be avoided with the trench structures in the termination area.

In this semiconductor device, a trench is formed on the upper surface of an n-type semiconductor layer laminated on a semiconductor substrate, a Schottky junction with metal is formed on the upper surface of an n-type region forming one side surface of the trench, and a pn junction is formed on the upper surface of an n-type region forming the other side surface of the trench. The pn junction is formed by a junction between the n-type region and the p-type semiconductor layer crystal-grown via epitaxial growth on the upper surface of the n-type region forming the other side surface.