Patent classifications
H01L29/882
Semiconductor device including two-dimensional material
A semiconductor device includes a substrate, a two-dimensional (2D) material layer formed on the substrate and having a first region and a second region adjacent to the first region, and a source electrode and a drain electrode provided to be respectively in contact with the first region and the second region of the 2D material layer, the second region of the 2D material layer including an oxygen adsorption material layer in which oxygen is adsorbed on a surface of the second region.
Compound semiconductor device and method for manufacturing the same
A compound semiconductor device includes: a substrate; a first barrier layer of a nitride semiconductor formed over the substrate; a well layer of a nitride semiconductor formed over the first barrier layer; and a second barrier layer of a nitride semiconductor formed over the well layer, wherein the first barrier layer, the well layer, and the second barrier layer each include a first region having, as an upper surface, a (0001) plane in terms of crystal orientation and a second region having, as an upper surface, a (000-1) plane in terms of crystal orientation, the first region of the first barrier layer, the first region of the well layer, and the first region of the second barrier layer are stacked, the second region of the first barrier layer, the second region of the well layer, and the second region of the second barrier layer are stacked.
Element, and oscillator and information acquiring device including the element
An element, including: a first conductor layer extending in a first direction; a second conductor layer extending in the first direction; and a semiconductor disposed between the first and second conductor layers, the semiconductor including: a first semiconductor layer in contact with the first conductor layer; a second semiconductor layer in contact with the second conductor layer; and an active layer disposed between the first and second semiconductor layers, in which: the semiconductor has a width of 0.5 m or more and 5 m or less in a direction intersecting the first and second directions, and has a thickness of 0.1 m or more and 1.0 m or less in the second direction; the active layer includes a double-barrier resonant tunnel diode; and each of the two barrier layers has a thickness of 0.7 nm or more and 2.0 nm or less in the second direction.
METHOD FOR MAKING A SEMICONDUCTOR DEVICE INCLUDING A RESONANT TUNNELING DIODE WITH ELECTRON MEAN FREE PATH CONTROL LAYERS
A method for making a semiconductor device may include forming at least one a double-barrier resonant tunneling diode (DBRTD) by forming a first doped semiconductor layer, and a forming first barrier layer on the first doped semiconductor layer and including a superlattice. The method may further include forming a first intrinsic semiconductor layer on the first barrier layer, forming a second barrier layer on the first intrinsic semiconductor layer and also comprising the superlattice, forming a second intrinsic semiconductor layer on the second barrier layer, and forming a third barrier layer on the second intrinsic semiconductor layer and also comprising the superlattice. The method may further include forming a third intrinsic semiconductor layer on the third barrier layer, forming a fourth barrier layer on the third intrinsic semiconductor layer, and forming a second doped semiconductor layer on the fourth barrier layer.
SEMICONDUCTOR DEVICE INCLUDING RESONANT TUNNELING DIODE STRUCTURE HAVING A SUPERLATTICE
A semiconductor device may include at least one double-barrier resonant tunneling diode (DBRTD). The at least one DBRTD may include a first doped semiconductor layer and a first barrier layer on the first doped semiconductor layer and including a superlattice. The superlattice may include stacked groups of layers, each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The at least one DBRTD may further include an intrinsic semiconductor layer on the first barrier layer, a second barrier layer on the intrinsic semiconductor layer, and a second doped semiconductor layer on the second superlattice layer.
METHOD FOR MAKING A SEMICONDUCTOR DEVICE INCLUDING A RESONANT TUNNELING DIODE STRUCTURE HAVING A SUPERLATTICE
A method for making a semiconductor device may include forming at least one double-barrier resonant tunneling diode (DBRTD) by forming a first doped semiconductor layer, and forming a first barrier layer on the first doped semiconductor layer and including a superlattice. The superlattice may include stacked groups of layers, each group of layers including stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming an intrinsic semiconductor layer on the first barrier layer, forming a second barrier layer on the intrinsic semiconductor layer, and forming a second doped semiconductor layer on the second superlattice layer.
SEMICONDUCTOR DEVICE INCLUDING A RESONANT TUNNELING DIODE STRUCTURE WITH ELECTRON MEAN FREE PATH CONTROL LAYERS
A semiconductor device including at least one double-barrier resonant tunneling diode (DBRTD) is provided. The at least one DBRTD may include a first doped semiconductor layer, and a first barrier layer on the first doped semiconductor layer and including a superlattice. The DBRTD may further include a first intrinsic semiconductor layer on the first barrier layer, a second barrier layer on the first intrinsic semiconductor layer and also including the superlattice, a second intrinsic semiconductor layer on the second barrier layer, a third barrier layer on the second intrinsic semiconductor layer and also including the superlattice. A third intrinsic semiconductor layer may be on the third barrier layer, a fourth barrier layer may be on the third intrinsic semiconductor layer and also including the superlattice, a second doped semiconductor layer on the fourth barrier layer.