A semiconductor device has: a semiconductor substrate; a trench that extends from a first surface of the semiconductor substrate towards an interior of the semiconductor substrate, and that has a recess/protrusion structure on a side wall surface thereof; a semiconductor film that is formed so as to cover the side wall surface of the trench, be continuous with the side wall surface, and extend onto the first surface of the semiconductor substrate; an opposite electrode having a first portion that is provided at a position opposing the semiconductor substrate while sandwiching the semiconductor film therebetween, and that extends on the first surface of the semiconductor substrate, and a second portion that is continuous with the first portion and extends so as to fill the trench; and an insulating film that insulates the semiconductor film from the opposite electrode.

A semiconductor device includes a first substrate having opposite first and second sides, a first conductive layer on the first side of the first substrate, and a second substrate having opposite first and second sides. The second side of the second substrate is bonded to the first side of the first substrate. The second substrate includes a semiconductor material, and at least one circuit element electrically coupled to the first conductive layer. The at least one circuit element includes at least one of a Schottky diode configured by the semiconductor material and a first contact structure, a capacitor having a first electrode of the semiconductor material, or a resistor of the semiconductor material.

There is disclosed herein an SOI IC comprising an integrated capacitor comprising a parallel arrangement of a metal-insulator-metal, MIM, capacitor, a second capacitor, a third capacitor, and a fourth capacitor: wherein the second capacitor comprises as plates the substrate and a one of a plurality of semiconductor layers having an n-type doping, and comprises the buried oxide layer as dielectric; the third capacitor comprises as plates the polysilicon layer and a further one of a plurality of semiconductor layers having an n-type doping, and comprises an insulating layer between the plurality of semiconductor layers and the metallisation stack as dielectric; and
the fourth capacitor comprises as plates the polysilicon plug and at least one of the plurality of semiconductor layers and comprises the oxide-lining as dielectric, wherein the oxide lining and the polysilicon plug form part of a lateral isolation (DTI) structure.

A semiconductor region includes an isolating region which delimits a working area of the semiconductor region. A trench is located in the working area and further extends into the isolating region. The trench is filled by an electrically conductive central portion that is insulated from the working area by an isolating enclosure. A cover region is positioned to cover at least a first part of the filled trench, wherein the first part is located in the working area. A dielectric layer is in contact with the filled trench. A metal silicide layer is located at least on the electrically conductive central portion of a second part of the filled trench, wherein the second part is not covered by the cover region.

A capacitor structure and method of forming the capacitor structure is provided, including a providing a doped region of a substrate having a two-dimensional trench array with a plurality of segments defined therein. Each of the plurality of segments has an array of a plurality of recesses extending along the substrate, where the plurality of segments are rotationally symmetric about a center of the two-dimensional trench array. A first conducting layer is presented over the surface and a bottom and sidewalls of the recesses and is insulated from the substrate by a first dielectric layer. A second conducting layer is presented over the first conducting layer and is insulated by a second dielectric layer. First and second contacts respectively connect to an exposed top surface of the first conducting layer and second conducting layer. A third contact connects to the substrate within a local region to the capacitor structure.

A method of making a semiconductor device includes etching a substrate to define a first trench and a second trench. The method further includes depositing a first number M of capacitor layer pairs in the first trench, wherein each of the first number M of capacitor layer pairs includes a first dielectric layer, and a first conductive layer. The method further includes depositing a second number N of capacitor layer pairs in the second trench, wherein the second number N is different from the first number M, and each of the second number N of capacitor layer pairs includes a second dielectric layer, and a second conductive layer. The method further includes planarizing the first number M of capacitor layer pairs and the second number N of capacitor layer pairs to expose the substrate.

The present disclosure, in some embodiments, relates to a metal-insulator-metal (MIM) capacitor structure. The MIM capacitor structure includes one or more lower interconnects disposed within a lower dielectric structure over a substrate. A first dielectric layer is over the lower dielectric structure and includes sidewalls defining a plurality of openings extending through the first dielectric layer. A lower electrode is arranged along the sidewalls and over an upper surface of the first dielectric layer, a capacitor dielectric is arranged along sidewalls and an upper surface of the lower electrode, and an upper electrode is arranged along sidewalls and an upper surface of the capacitor dielectric. A spacer is along opposing outermost sidewalls of the upper electrode. The spacer has an outermost surface extending from a lowermost surface of the spacer to a top of the spacer. The outermost surface is substantially aligned with an outermost sidewall of the lower electrode.

In some embodiments, the present disclosure relates to an integrated circuit (IC), including a first insulating layer which includes a first metal interconnect structure stacked above a bottom die. Including a substrate disposed above the first insulating layer, a second metal interconnect structure disposed above the substrate, a through-substrate via (TSV) directly connecting the first metal interconnect structure to the second metal interconnect structure, and a stacked deep trench capacitor (DTC) structure disposed in the substrate. The DTC structure includes a first plurality of trenches extending from a first side of the substrate and a second plurality of trenches extending from a second side of the substrate.

A semiconductor trench capacitor structure is provided. The semiconductor trench capacitor comprises a semiconductor substrate; a trench capacitor overlying the semiconductor substrate, wherein the trench capacitor comprises a plurality of trench electrodes and a plurality of capacitor dielectric layers that are alternatingly stacked over the semiconductor substrate and defines a plurality of trench segments and a plurality of pillar segments, wherein the trench electrodes and the capacitor dielectric layers are recessed into the semiconductor substrate at the trench segments, and wherein the trench segments are separated from each other by the pillar segments; and a protection dielectric layer disposed between the semiconductor substrate and the trench capacitor, wherein the protection dielectric layer has a thickness greater than thicknesses of the trench electrodes.

Some implementations described herein provide a semiconductor device and methods of formation. The semiconductor device may include a photodiode device electrically connected to a metal-insulator-metal deep-trench capacitor. The metal-insulator-metal deep-trench capacitor includes a layer of an amorphous material between an insulator layer stack of the deep-trench capacitor structure and a capacitor bottom metal layer of the metal-insulator-metal deep-trench capacitor. The amorphous material includes a bandgap energy level that provides a conduction band offset and lowers a probability of electron tunneling from the capacitor bottom metal electrode layer to the insulator layer stack. In this way, leakage associated with grain boundaries, crystal defects, and interfaces of a bottom layer of the insulator layer stack may be overcome to improve a lag performance of the semiconductor device including the metal-insulator-metal deep-trench capacitor.