A semiconductor device includes a substrate including a first trench that extends along a first lateral direction and a second trench that extends along a second lateral direction; a first metal layer filling each of the first and second trenches; a second metal layer filling each of the first and second trenches, and disposed above and electrically isolated from the first metal layer; a first via structure in electrical contact with first metal layer; and a second via structure in electrical contact with second metal layer. When viewed from the top, the first via structure and the second via structure are interposed between the first trench and the second trench along the first lateral direction. The first via structure and the second via structure are disposed immediately adjacent to each other along the second lateral direction.

A semiconductor device has: a semiconductor substrate; a trench that extends from a first surface of the semiconductor substrate towards an interior of the semiconductor substrate, and that has a recess/protrusion structure on a side wall surface thereof; a semiconductor film that is formed so as to cover the side wall surface of the trench, be continuous with the side wall surface, and extend onto the first surface of the semiconductor substrate; an opposite electrode having a first portion that is provided at a position opposing the semiconductor substrate while sandwiching the semiconductor film therebetween, and that extends on the first surface of the semiconductor substrate, and a second portion that is continuous with the first portion and extends so as to fill the trench; and an insulating film that insulates the semiconductor film from the opposite electrode.

Various embodiments of the present disclosure are directed towards an integrated chip including a capacitor over a substrate. The capacitor includes a plurality of conductive layers and a plurality of dielectric layers. The plurality of conductive layers and dielectric layers define a base structure and a first protrusion structure extending downward from the base structure towards a bottom surface of the substrate. The first protrusion structure comprises one or more surfaces defining a first cavity. A top of the first cavity is disposed below the base structure.

A semiconductor device is provided that includes a semiconductor substrate having a first main surface and a second main surface facing each other; a dielectric layer laminated on the first main surface of the semiconductor substrate; a first electrode layer laminated on the dielectric layer; and a protective layer covering at least an outer peripheral end of the dielectric layer and an outer peripheral end of the first electrode layer. Moreover, the protective layer is provided to expose an outer peripheral end on the first main surface of the semiconductor substrate. The semiconductor substrate includes a high-resistance region positioned at least directly under an outer peripheral end of the protective layer.

The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a semiconductor substrate having sidewalls that define a recess within an upper surface of the semiconductor substrate. A plurality of upper electrode segments are arranged over the semiconductor substrate and are vertically separated from the upper surface of the semiconductor substrate by a first dielectric layer. A lower electrode segment is arranged directly between the sidewalls of the semiconductor substrate and directly between adjacent ones of the plurality of upper electrode segments. A second dielectric layer is arranged directly between the sidewalls of the semiconductor substrate and the lower electrode segment and also directly between the plurality of upper electrode segments and the lower electrode segment.

A semiconductor device and a method of manufacturing the semiconductor device are disclosed. In one aspect, the semiconductor device includes a plurality of deep trench capacitors and a plurality of via contacts that at least partially surround the deep trench capacitors. Variations may be made to the number and locations of the plurality of via contacts such that design requirements for the packaging are satisfied.

A device includes a substrate including a low-resistance top surface and a fin structure including a first fin and a second fin. Each of the first and second fins includes a low-resistance fin-top surface and two low-resistance sidewall surfaces. The device includes an insulation material over the top surface of the substrate and between the first fin and the second fin. The fin-top surface and a first portion of the sidewall surfaces of each of the first and the second fins are above the insulation material. The device further includes a dielectric layer over the insulation material and in direct contact with the fin-top surface and the first portion of the sidewall surfaces of each of the first and the second fins; a first electrode in direct contact with the fin-top surface of the first fin; and a second electrode over the dielectric layer that is over the second fin.

A semiconductor device including field-effect transistors (finFETs) and fin capacitors are formed on a silicon substrate. The fin capacitors include silicon fins, one or more electrical conductors between the silicon fins, and insulating material between the silicon fins and the one or more electrical conductors. The fin capacitors may also include insulating material between the one or more electrical conductors and underlying semiconductor material.

Various embodiments of the present disclosure are directed towards a trench capacitor with a trench pattern for yield improvement. The trench capacitor is on a substrate and comprises a plurality of capacitor segments. The capacitor segments extend into the substrate according to the trench pattern and are spaced with a pitch on an axis. The plurality of capacitor segments comprises an edge capacitor segment at an edge of the trench capacitor and a center capacitor segment at a center of the trench capacitor. The edge capacitor segment has a greater width than the center capacitor segment and/or the pitch is greater at the edge capacitor segment than at the center capacitor segment. The greater width may facilitate stress absorption and the greater pitch may increase substrate rigidity at the edge of the trench capacitor where thermal expansion stress is greatest, thereby reducing substrate bending and trench burnout for yield improvements.

A three-dimensional capacitor component that includes a substrate having a textured (contoured) surface and a stack of layers formed conformally over the textured surface to constitute a capacitive stack structure. Respective contacts to the bottom and top electrodes of the capacitive stack structure are both provided at a first side of the component. The bottom electrode and substrate are doped with dopants of the same polarity, and the substrate is heavily doped so that current between a terminal portion of the bottom electrode and remote parts of the bottom electrode flows via the substrate, lowering ESR. A backside metallization layer produces a further, and greater, reduction in ESR. The capacitor component may be implemented as a discrete capacitor component, but may also be integrated with other components/devices. Corresponding fabrication methods are described.