A structural body according to an embodiment includes a conductive substrate. A main surface of the conductive substrate includes a first region and a second region adjacent to the first region and lower in height than the first region. The first region is provided with one or more recesses having a bottom, a position of which is lower than a position of the second region. A surface region of the conductive substrate on a side of the main surface includes a porous structure at a position between the second region and the one or more recesses.

A semiconductor wafer manufacturing method including: forming a plurality of trench capacitors at a main surface of a semiconductor wafer, wherein each of the plurality of trench capacitors is configured as unit cells that internally include unit trench capacitors, and wherein a length component in a predetermined direction of a layout pattern of trenches of the plurality of trench capacitors is made equivalent, within a fixed tolerance range, to a length component in a direction that intersects the predetermined direction.

Various embodiments of the present disclosure are directed towards a trench capacitor with a trench pattern for yield improvement. The trench capacitor is on a substrate and comprises a plurality of capacitor segments. The capacitor segments extend into the substrate according to the trench pattern and are spaced with a pitch on an axis. The plurality of capacitor segments comprises an edge capacitor segment at an edge of the trench capacitor and a center capacitor segment at a center of the trench capacitor. The edge capacitor segment has a greater width than the center capacitor segment and/or the pitch is greater at the edge capacitor segment than at the center capacitor segment. The greater width may facilitate stress absorption and the greater pitch may increase substrate rigidity at the edge of the trench capacitor where thermal expansion stress is greatest, thereby reducing substrate bending and trench burnout for yield improvements.

A capacitor structure is provided, which includes a contact layer, an insulating layer, a bottom conductive plate, a dielectric layer and a top conductive plate. The contact layer has first, second, third, fourth and fifth portions arranged from periphery to center. The insulating layer is disposed over the contact layer and has an opening exposing the contact layer. The bottom conductive plate is disposed in the opening and including first, second and third portions extending along a depth direction of the opening and separated from each other and in contact with the first, third and fifth portions of the contact layer, respectively. The dielectric layer is conformally disposed on the bottom conductive plate and in contact with the second and fourth portions of the contact layer. The top conductive plate is disposed on the dielectric layer. A method of manufacturing the capacitor is also provided.

The present disclosure provides a chip part. The chip part includes a substrate, a first external electrode, a second external electrode, a capacitor portion, a lower electrode, a capacitive film and an upper electrode. The first external electrode and the second external electrode are disposed on a first main surface of the substrate. The capacitor portion is disposed on the first main surface of the substrate. The lower electrode includes a first body portion and a first peripheral portion integrally drawn out around the capacitor portion from the first body portion. The capacitive film includes a second body portion disposed within the capacitor portion and a second peripheral portion integrally drawn out from the second body portion to the first peripheral portion. The upper electrode is disposed on the capacitive film.

The present disclosure provides a chip part. The chip part includes: a capacitor portion, including a plurality of wall portions separated from each other by a plurality of trenches formed on the first main surface and having a lengthwise direction; a substrate body, formed around the capacitor portion using a portion of the semiconductor substrate; a lower electrode, disposed using at least a portion of the semiconductor substrate including the wall portions; a capacitive film, disposed along top and side surfaces of the plurality of wall portions; and an upper electrode, disposed on the capacitive film.

A method for manufacturing a semiconductor structure, a semiconductor structure, and a capacitor structure are provided. The method includes: providing a substrate, a plurality of blind holes or grooves being provided in a surface of the substrate; forming filling layers in the plurality of blind holes or grooves, top surfaces of the filling layers being flush with a top surface of the substrate; and forming a cap layer on the top surfaces of the filling layers and the top surface of the substrate, in which the cap layer includes at least a film-stacked structure, the film-stacked structure includes a first cap film and a second cap film, and a doping material source of the first cap film is different from a doping material source of the second cap film.

The present disclosure relates to an integrated chip including a dielectric structure over a substrate. A first capacitor is disposed between sidewalls of the dielectric structure. The first capacitor includes a first electrode between the sidewalls of the dielectric structure and a second electrode between the sidewalls and over the first electrode. A second capacitor is disposed between the sidewalls. The second capacitor includes the second electrode and a third electrode between the sidewalls and over the second electrode. A third capacitor is disposed between the sidewalls. The third capacitor includes the third electrode and a fourth electrode between the sidewalls and over the third electrode. The first capacitor, the second capacitor, and the third capacitor are coupled in parallel by a first contact on a first side of the first capacitor and a second contact on a second side of the first capacitor.

A capacitor includes: a substrate; a first trench entering the substrate downward from the upper surface of the substrate; a laminated structure provided in the first trench and including m dielectric layers and n conductive layers, the m dielectric layers and the n conductive layers forming a structure that a conductive layer and a dielectric layer are adjacent to each other, each dielectric layer of the m dielectric layers including at least one high-k insulating material with a relative dielectric constant k greater than a first threshold value, and each conductive layer of the n conductive layers including at least one high work function conductive material with a work function greater than a second threshold value, where m and n are positive integers; and a first electrode electrically connected to all odd-numbered conductive layers, and a second electrode electrically connected to all even-numbered conductive layers.

Disclosed are devices having a metal-insulator-metal (MIM) capacitor and methods for fabricating the devices. The MIM capacitor includes a plurality of trenches in a Silicon (Si) substrate; a porous Si surface formed in the plurality of trenches, where the porous Si surface has an irregular surface on sidewalls and bottoms of the plurality of trenches; an oxide layer conformally disposed on the porous Si surface; a first plate conformally disposed on the oxide layer; a first dielectric layer conformally disposed on the first plate; and a second plate conformally disposed on the first dielectric, where the first plate, the first dielectric layer, and the second plate, each have an irregular surface that generally conforms to the irregular surface of the porous Si surface.