A multi-voltage domain device includes a semiconductor layer including a first main surface, a second main surface arranged opposite to the first main surface, a first region including first circuitry that operates in a first voltage domain, a second region including second circuitry that operates in a second voltage domain different than the first voltage domain, and an isolation region that electrically isolates the first region from the second region in a lateral direction that extends parallel to the first and the second main surfaces. The isolation region includes at least one deep trench isolation barrier, each of which extends vertically from the first main surface to the second main surface. The multi-voltage domain device further includes at least one first capacitor configured to generate an electric field laterally across the isolation region between the first region and the second region.

A capacitor structure and method of forming the capacitor structure is provided, including a providing a doped region of a substrate having a two-dimensional trench array with a plurality of segments defined therein. Each of the plurality of segments has an array of a plurality of recesses extending along the substrate, where the plurality of segments are rotationally symmetric about a center of the two-dimensional trench array. A first conducting layer is presented over the surface and a bottom and sidewalls of the recesses and is insulated from the substrate by a first dielectric layer. A second conducting layer is presented over the first conducting layer and is insulated by a second dielectric layer. First and second contacts respectively connect to an exposed top surface of the first conducting layer and second conducting layer. A third contact connects to the substrate within a local region to the capacitor structure.

A method for forming a poly-insulator-poly (PIP) capacitor is disclosed. A semiconductor substrate having a capacitor forming region is provided. A first capacitor dielectric layer is formed on the capacitor forming region. A first poly electrode is formed on the first capacitor dielectric layer. A second capacitor dielectric layer is formed on the first poly electrode. A second poly electrode is formed on the second capacitor dielectric layer. A third poly electrode is formed adjacent to a first sidewall of the second poly electrode. A third capacitor dielectric layer is formed between the third poly electrode and the second poly electrode. A fourth poly electrode is formed adjacent to a second sidewall of the second poly electrode that is opposite to the first sidewall. A fourth capacitor dielectric layer is formed between the fourth poly electrode and the second poly electrode.

An electronic device includes a semiconductor memory. The semiconductor memory may include a semiconductor substrate having an isolation trench in a first region and a capacitor trench in a second region, an isolation layer filling the isolation trench, an insulation layer pattern disposed along the capacitor trench, and a conductive layer pattern filling the capacitor trench over the insulation layer pattern. A capacitor includes a first portion of the semiconductor substrate in the second region, the insulation layer pattern, and the conductive pattern. A sidewall of the capacitor trench has a first angle with respect to a surface of the semiconductor substrate and a sidewall of the isolation trench has a second angle with respect to the surface of the semiconductor substrate. The first angle is more proximate to 90 degrees than the second angle.

A capacitor includes a silicon substrate, a conductor layer, and a dielectric layer. The silicon substrate has a principal surface including a capacitance generation region and a non-capacitance generation region. The silicon substrate includes a porous part provided in a thickness direction in the capacitance generation region. The conductor layer includes a surface layer part at least covering part of a surface of the capacitance generation region and a filling part filled in at least part of the porous part. The dielectric layer is provided between an inner surface of the porous part and the filling part. The porous part includes a macroporous part having macro pores and a nanoporous part formed in at least part of inner surfaces of the macro pores and having nano pores smaller than the macro pores.

An image sensor includes: a pixel chip provided with a plurality of pixels, a plurality of first transfer lines, and a plurality of capacitors; a circuit chip provided with a plurality of column reading circuits, a plurality of column scanning circuits, a second transfer line, and a constant current source; and a connection portion stacked and provided between the pixel chip and the circuit chip and configured to connect a capacitor, which is arranged in the pixel chip and has a trench structure, and a first transistor arranged in the circuit chip to each other via an electrode. The capacitor is configured to form a transfer capacity removing a noise included in an imaging signal and connect the pixel chip and the circuit chip to each other via the electrode and the connection portion.

The stack capacitor structure includes a substrate, first, second, third, and fourth support layers, first, second, and third insulating layers, first, second, and third holes, and a capacitor. The first support layer is disposed over the substrate. The first insulating layer is disposed on the first support layer. The second support layer is disposed on the first insulating layer. The third support layer is disposed on the second support layer. The second insulating layer is disposed on the third support layer. The third insulating layer is disposed on the second insulating layer. The fourth support layer is disposed on the third insulating layer. The first hole penetrates through from the second support layer to the first support layer. The second and third holes penetrate through from the fourth support layer to the third support layer. The capacitor is disposed in the first, second, and third holes.

An electronic device can include one or more trenches that include a material that defines one or more voids. In an embodiment, the substrate defines a first trench having a first portion and a second portion laterally adjacent to the first portion, wherein the first portion has with a first width, the second portion has a second width, and the first width is wider than the second width. The material defines a first void at a predetermined location within the first portion of the first trench and has a seam within the second portion of the first trench. In another embodiment, the substrate defining a trench, and the material that defines spaced-apart voids at predetermined locations within the trench. A process of forming the electronic device can include patterning a substrate to define a trench, and depositing a material within the trench, wherein the deposited material defines a void.

A multi-voltage domain device includes a semiconductor layer including a first main surface, a second main surface arranged opposite to the first main surface, a first region including first circuity that operates in a first voltage domain, a second region including second circuity that operates in a second voltage domain different than the first voltage domain, and an isolation region that electrically isolates the first region from the second region in a lateral direction that extends parallel to the first and the second main surfaces. The isolation region includes at least one deep trench isolation barrier, each of which extends vertically from the first main surface to the second main surface. The multi-voltage domain device further includes at least one first capacitor configured to generate an electric field laterally across the isolation region between the first region and the second region.

An integrated circuit including a trench in the substrate with a high quality trench oxide grown on the sidewalls and the bottom of the trench where the ratio of the thickness of the high quality trench oxide formed on the sidewalls to the thickness formed on the bottom is less than 1.2. An integrated circuit including a trench with high quality oxide is formed by first growing a sacrificial oxide in dilute oxygen at a temperature in the range of 1050° C. to 1250° C., stripping the sacrificial oxide, growing high quality oxide in dilute oxygen plus trans 1,2 dichloroethylene at a temperature in the range of 1050° C. to 1250° C., and annealing the high quality oxide in an inert ambient at a temperature in the range of 1050° C. to 1250° C.