A solar cell includes a top cell module that generates power by photoelectrically converting incident light and allows part of the incident light to pass through the top cell module, and a bottom cell module that is laminated to the top cell module and generates power by photoelectrically converting light that has passed through the top cell module, wherein the top cell module includes a plurality of top cells that are connected in series, in parallel, or in a combination of series and parallel, the bottom cell module includes a plurality of bottom cells that are connected in series, in parallel, or in a combination of series and parallel, the number of the bottom cells being equal to the number of the top cells, and an electrode connecting the plurality of top cells is positioned such that the electrode does not overlap the bottom cells in plan view.

The present application relates to the field of solar cells, and in particular to a main-gate-free and high-efficiency back-contact solar cell module, assembly, and a preparation process thereof. The main-gate-free and high-efficiency back-contact solar cell module comprises solar cells and an electrical connection layer, a backlight side of the solar cells having P-electrodes connected to a P-type doping layer and N-electrodes connected to an N-type doping layer, wherein the electrical connection layer comprises a number of small conductive gate lines, part of which are connected to the P-electrodes on the backlight side of the solar cells while the other part of which are connected to the N-electrodes on the backlight side of the solar cells; and, the small conductive gate lines are of a multi-section structure. The present application has the following beneficial effects: the usage of silver paste is decreased, and the cost is reduced; moreover. The arrangement of small conductive gate lines in a multi-section structure reduces the series resistance and the transmission distance of a filling factor, so that the efficiency is improved and the stress on the cells from the small conductive gate lines can be effectively reduced.

A method for producing a multiplicity of semiconductor chips (13) is provided, comprising the following steps: providing a wafer (1) comprising a multiplicity of semiconductor bodies (2), wherein separating lines (9) are arranged between the semiconductor bodies (2), depositing a contact layer (10) on the wafer (1), wherein the material of the contact layer (10) is chosen from the following group: platinum, rhodium, palladium, gold, and the contact layer (10) has a thickness of between 8 nanometres and 250 nanometres, inclusive, applying; the wafer (1) to a film (11), at least partially severing the wafer (1) in the vertical direction along the separating lines (9) or introducing fracture nuclei (12) into the wafer (1) along the separating lines (9), and breaking the wafer (1) along the separating lines (9) or expanding the film (11) such that a spatial separation of the semiconductor chips (13) takes place, wherein the contact layer (10) is also separated. A semiconductor chip, a component and a method for producing the latter are also provided.

The disclosure provides an electrode structure of a back contact cell, a back contact cell, a back contact cell module, and a back contact cell system. The electrode structure includes: first fingers, configured to collect a first polarity region; second fingers, configured to collect a second polarity region; a first busbar, disposed on a side of the back contact cell close to a first edge and connected to the first fingers; first pad points; and first connection electrodes, respectively connected to the first busbar and the first pad points. A distance between each of the first pad points and the first edge is greater than a distance between the first busbar and the first edge. The electrode structure can improve the reliability, reduce the costs, increase the product yield, and ensure excellent photoelectric conversion efficiency.

Solar cells having emitter regions composed of wide bandgap semiconductor material are described. In an example, a method includes forming, in a process tool having a controlled atmosphere, a thin dielectric layer on a surface of a semiconductor substrate of the solar cell. The semiconductor substrate has a bandgap. Without removing the semiconductor substrate from the controlled atmosphere of the process tool, a semiconductor layer is formed on the thin dielectric layer. The semiconductor layer has a bandgap at least approximately 0.2 electron Volts (eV) above the bandgap of the semiconductor substrate.

A solar cell, having a front side which faces the sun during normal operation, and a back side opposite the front side can include a silicon substrate having doped regions and a polysilicon layer disposed over the doped regions. The solar cell can include a conductive filling formed between a first metal layer and doped regions and through or at least partially through the polysilicon layer, where the conductive filling electrically couples the first metal layer and the doped region. In an embodiment, a second metal layer is formed on the first metal layer, where the first metal layer and the conductive filling electrically couple the doped regions and the second metal layer. In some embodiments, the solar cell can be a front contact solar cell or a back contact solar cell.

The disclosure relates to the technical field of solar cells, and provides a solar cell and a doped region structure thereof, a cell assembly, and a photovoltaic system. The doped region structure includes a first doped layer, a passivation layer, and a second doped layer that are disposed on a silicon substrate in sequence. The passivation layer is a porous structure having the first doped layer and/or the second doped layer inlaid in a hole region. The first doped layer and the second doped layer have a same doping polarity. By means of the doped region structure of the solar cell provided in the disclosure, the difficulty in production and the limitation on conversion efficiency as a result of precise requirements for the accuracy of a thickness of a conventional tunneling layer are resolved.

Fabrication methods and structures relating to backplanes for back contact solar cells that provide for solar cell substrate reinforcement and electrical interconnects as well as Fabrication methods and structures for forming thin film back contact solar cells are described.

A method for fabricating a solar cell and the and the resulting structures, e.g., micro-electronic devices, semiconductor substrates and/or solar cells, are described. The method can include: providing a solar cell having metal foil having first regions that are electrically connected to semiconductor regions on a substrate at a plurality of conductive contact structures, and second regions; locating a carrier sheet over the second regions; bonding the carrier sheet to the second regions; and removing the carrier sheet from the substrate to selectively remove the second regions of the metal foil.

A solar cell, and methods of fabricating said solar cell, are disclosed. The solar cell can include a substrate having a light-receiving surface and a back surface. The solar cell can include a first semiconductor region of a first conductivity type disposed on a first dielectric layer, wherein the first dielectric layer is disposed on the substrate. The solar cell can also include a second semiconductor region of a second, different, conductivity type disposed on a second dielectric layer, where a portion of the second thin dielectric layer is disposed between the first and second semiconductor regions. The solar cell can include a third dielectric layer disposed on the second semiconductor region. The solar cell can include a first conductive contact disposed over the first semiconductor region but not the third dielectric layer. The solar cell can include a second conductive contact disposed over the second semiconductor region, where the second conductive contact is disposed over the third dielectric layer and second semiconductor region. In an embodiment, the third dielectric layer can be a dopant layer.