According to the embodiments provided herein, a method for forming a photovoltaic device can include depositing a plurality of semiconductor layers. The plurality of semiconductor layers can include a doped layer that is doped with a group V dopant. The doped layer can include cadmium selenide or cadmium telluride. The method can include annealing the plurality of semiconductor layers to form an absorber layer.

A doped photovoltaic device is presented. The photovoltaic device includes a semiconductor absorber layer or stack disposed between a front contact and a back contact. The absorber layer comprises cadmium, selenium, and tellurium doped with Ag, and optionally with Cu. The Ag dopant may be added to the absorber in amounts ranging from 5×10.sup.15/cm.sup.3 to 2.5×10.sup.17/cm.sup.3 via any of several methods of application before, during, or after deposition of the absorber layer. The photovoltaic device has improved Fill Factor and P.sub.MAX at higher P.sub.r(=I.sub.sc*V.sub.oc product) values, e.g. about 160 W, which results in improved conversion efficiency compared to a device not doped with Ag. Improved PT may result from increased I.sub.sc, increased V.sub.oc, or both.

Photo-detector comprising: photo absorbing layer exhibiting a valence band energy level; a barrier layer, first side of the barrier layer adjacent a first side of the photo absorbing layer, the barrier layer exhibiting a valence band energy level substantially equal to the valence band energy level of the photo absorbing layer; and a contact area comprising a doped semiconductor, the contact area being adjacent a second side of the barrier layer opposing the first side, the barrier layer exhibiting a thickness and a conductance band gap sufficient to prevent tunneling of majority carriers between the photo absorbing layer and contact area, and block the flow of thermalized majority carriers between the photo absorbing layer and contact area. The photoabsorber layer extends past the one or more individual sections of the contact layer in the direction across the photodetector, and is monolithically provided for each of the individuals detector elements.

Disclosed herein are compositions and methods for making polycrystalline thin films having very large grains sizes and exhibiting improved properties over existing thin films.

Disclosed herein is an apparatus and a method of making the apparatus. The method comprises obtaining a plurality of semiconductor single crystal chunks. Each of the plurality of semiconductor single crystal chunks may have a first surface and a second surface. The second surface may be opposite to the first surface. The method may further comprise bonding the plurality of semiconductor single crystal chunks by respective first surfaces to a first semiconductor wafer. The plurality of semiconductor single crystal chunks forming a radiation absorption layer. The method may further comprise forming a plurality of electrodes on respective second surfaces of each of the plurality of semiconductor single crystal chunks, depositing pillars on each of the plurality of semiconductor single crystal chunks and bonding the plurality of semiconductor single crystal chunks to a second semiconductor wafer by the pillars.

Provided is a radiation detection element, including: a plurality of electrode portions on a surface of a substrate; and an insulating portion between the electrode portions, the substrate being made of a compound semiconductor crystal containing cadmium telluride or cadmium zinc telluride, wherein an intermediate layer containing tellurium oxide is present between each of the electrode portions and the substrate, and wherein the tellurium oxide layer has a thickness of 100 nm or less on a 500 nm inner side from an end portion of the insulating portion between the electrode portions. The radiation detection element has higher adhesion of the electrodes, and does not result in an element performance defect caused by insufficient insulation between the electrodes, even if the radiation detection element has a narrower distance between the electrode portions in order to obtain a high-definition radiographic image.

The present invention proposes a method to form a double-graded CdSeTe thin film. The method comprises providing a base substrate, forming a first CdSe.sub.wTe.sub.1-w layer having a first amount w1 of selenium in it, forming a second CdSe.sub.wTe.sub.1-w layer having a second amount w2 of selenium in it and forming a third CdSe.sub.wTe.sub.1-w layer having a third amount w3 of selenium in it. The second amount w2 lies in the range between 0.25 and 0.4, whereas each of the amounts w1 and w3 lies in the range extending from 0 to 1. According to the present invention, the energy gap in the first and the third CdSe.sub.wTe.sub.1-w layers is equal to or higher than 1.45 eV and the energy gap in the second CdSe.sub.wTe.sub.1-w layer lies in the range between 1.38 eV and 1.45 eV and is smaller than the energy gap in the first and the third CdSe.sub.wTe.sub.1-w layers.

An integrated circuit includes a photodetector. The photodetector includes one or more dielectric structures positioned in a trench in a semiconductor substrate. The photodetector includes a photosensitive material positioned in the trench and covering the one or more dielectric structures. A dielectric layer covers the photosensitive material. The photosensitive material has an index of refraction that is greater than the indices of refraction of the dielectric structures and the dielectric layer.

A photodetector includes an UV transparent n-type structure, an UV transparent p-type structure, and a photon absorbing region sandwiched between the n-type structure and the p-type structure; a p-contact layer formed on the p-type structure; and a p-ohmic contact of a thickness in the range of 0.2-100 nm formed on the p-contact layer, wherein the p-ohmic contact comprises one or more layer of metal oxide.

An electrical device includes a substrate, an insulating layer supported by the substrate, and an electrically conductive vertical interconnect disposed in a via hole of the insulating layer. The insulating layer may be configured to provide a coefficient of thermal expansion (CTE) that is equal to or greater than a CTE of the vertical interconnect to thereby impart axial compressive forces at opposite ends of the interconnect. The vertical interconnect may be a hybrid interconnect structure including a low CTE conductor post having a pocket that contains a high CTE conductor contact. At low operating temperatures, the high CTE conductor contact is under tension due to the higher CTE, and thus the high CTE conductor contact relieves strain in the device by void expansion and elongation.