H01L31/1105

ISOLATOR INTEGRATED CIRCUITS WITH PACKAGE STRUCTURE CAVITY AND FABRICATION METHODS

In described examples, an integrated circuit includes a leadframe structure, which includes electrical conductors. A first coil structure is electrically connected to a first pair of the electrical conductors of the leadframe structure. The first coil structure is partially formed on a semiconductor die structure. A second coil structure is electrically connected to a second pair of the electrical conductors of the leadframe structure. The second coil structure is partially formed on the semiconductor die structure. A molded package structure encloses portions of the leadframe structure. The molded package structure exposes portions of the first and second pairs of the electrical conductors to allow external connection to the first and second coil structures. The molded package structure includes a cavity to magnetically couple portions of the first and second coil structures.

Silicon-germanium photoelectric detection apparatus based on on-chip mode converter

An on-chip mode converter-based silicon-germanium photoelectric detection apparatus comprises an insulating substrate, an optical coupler, an on-chip mode converter and a multi-mode silicon-germanium photoelectric detector. The optical coupler, the converter and the photoelectric detector are sequentially connected and all fixed on silicon wafers of the insulating substrate. An incident fundamental mode optical signal is transmitted to the optical coupler through a single-mode fiber, enters the converter via the optical coupled. The converter converts the fundamental mode optical signal into a multi-mode optical field and enters the photoelectric detector, which converts the multi-mode optical field into an electrical signal. Heavily germanium-doped region are located in areas with relatively weak distributed light intensity of the multi-mode optical field. The absorption loss of the heavily germanium-doped region and third through-holes on the optical field is dramatically reduced and the responsiveness of the apparatus can be improved effectively.

SEMICONDUCTOR DEVICE WITH SINGLE ELECTRON COUNTING CAPABILITY
20200212245 · 2020-07-02 ·

The semiconductor device comprises a bipolar transistor with emitter, base and collector, a current or voltage source electrically connected with the emitter, and a quenching component electrically connected with the collector, the bipolar transistor being configured for operation at a collector-to-base voltage above the breakdown voltage.

Method And System For Optoelectronic Receivers Utilizing Waveguide Heterojunction Phototransistors Integrated In A CMOS SOI Wafer
20200177284 · 2020-06-04 ·

A method and system for optoelectronic receivers utilizing waveguide heterojunction phototransistors (HPTs) integrated in a wafer are disclosed and may include receiving optical signals via optical fibers operably coupled to a top surface of the chip. Electrical signals may be generated utilizing HPTs that detect the optical signals. The electrical signals may be amplified via voltage amplifiers, or transimpedance amplifiers, the outputs of which may be utilized to bias the HPTs by a feedback network. The optical signals may be coupled into opposite ends of the HPTs. A collector of the HPTs may comprise a silicon layer and a germanium layer, a base may comprise a silicon germanium alloy with germanium composition ranging from 70% to 100%, and an emitter including crystalline or poly Si or SiGe.

Photosensitive semiconductor component, method for forming a photosensitive semiconductor component
11876144 · 2024-01-16 · ·

A photosensitive transistor is disclosed herein that includes: a semiconductor substrate of the first conductivity type as a collector layer; above it a less doped layer of the first conductivity type having regions of different thickness; a semiconductor base layer of the second conductivity type above at least parts of the regions of the less doped layer; and an emitter layer of the first conductivity type above at least parts of the base layer, but not above at least one part of the part of the base layer disposed above the thinner region of the less doped layer.

Isolator integrated circuits with package structure cavity and fabrication methods

In described examples, an integrated circuit includes a leadframe structure, which includes electrical conductors. A first coil structure is electrically connected to a first pair of the electrical conductors of the leadframe structure. The first coil structure is partially formed on a semiconductor die structure. A second coil structure is electrically connected to a second pair of the electrical conductors of the leadframe structure. The second coil structure is partially formed on the semiconductor die structure. A molded package structure encloses portions of the leadframe structure. The molded package structure exposes portions of the first and second pairs of the electrical conductors to allow external connection to the first and second coil structures. The molded package structure includes a cavity to magnetically couple portions of the first and second coil structures.

VOLTAGE TUNABLE SOLAR BLINDNESS IN TFS GROWN EG/SIC SCHOTTKY CONTACT BIPOLAR PHOTOTRANSISTORS

A voltage tunable solar-blind UV detector using a EG/SiC heterojunction based Schottky emitter bipolar phototransistor with EG grown on p-SiC epi-layer using a chemically accelerated selective etching process of Si using TFS precursor.

Dual wavelength hybrid device
10601198 · 2020-03-24 · ·

A Dual-wavelength hybrid (DWH) device includes an n-type ohmic contact layer, cathode and anode terminal electrodes, first and second injector terminal electrodes, p-type and n-type modulation doped QW structures, and first through sixth ion implant regions. The first injector terminal electrode is formed on the third ion implant region that contacts the p-type modulation doped QW structure and the second injector terminal electrode is formed on the fourth ion implant region that contacts the n-type modulation doped QW structure. The DWH device operates in at least one of a vertical cavity mode and a whispering gallery mode. In the vertical cavity mode, the DWH device converts an in-plane optical mode signal to a vertical optical mode signal, whereas in the whispering gallery mode the DWH device converts a vertical optical mode signal to an in-plane optical mode signal.

Bi CMOS pixel
10573775 · 2020-02-25 ·

A bipolar complementary metal oxide semiconductor three transistor pixel with P-type metal-oxide-semiconductor base discharge and N-type metal-oxide-semiconductor emitter blocking.

OPTOELECTRONIC SEMICONDUCTOR STRUCTURE HAVING A BIPOLAR PHOTOTRANSISTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

An optoelectronic semiconductor structure includes a first n-type semiconductor layer, a first quantum well layer, a first p-type semiconductor layer, and a second n-type semiconductor layer. The first quantum well layer is disposed on the first n-type semiconductor layer. The first p-type semiconductor layer is disposed on the first quantum well layer. The second n-type semiconductor layer is disposed on the first p-type semiconductor layer. The second n-type semiconductor layer includes both an n-type dopant and a p-type dopant. The concentration of the n-type dopant in the second n-type semiconductor layer is greater than the concentration of the p-type dopant in the second n-type semiconductor layer. The first n-type semiconductor layer, the first quantum well layer, the first p-type semiconductor layer, and the second n-type semiconductor layer form a bipolar phototransistor structure. A manufacturing method of the optoelectronic semiconductor structure is also provided.