The present disclosure provides an optical sensing device, including: a storage circuitry being coupled to a charging circuitry, a photosensitive circuitry, and a voltage-readout circuitry, the storage circuitry storing a voltage value; the charging circuitry being coupled to the storage circuitry for charging the storage circuitry; the photosensitive circuitry being connected to a first terminal for discharging the storage circuitry to the first terminal; and the voltage-readout circuitry being connected to the storage circuitry, for reading the voltage value of the storage circuitry.

Nanocomposites in accordance with many embodiments of the invention can be capable of converting electromagnetic radiation to an electric signal, such as signals in the form of current or voltage. In some embodiments, metallic nanostructures are integrated with graphene material to form a metallo-graphene nanocomposite. Graphene is a material that has been explored for broadband and ultrafast photodetection applications because of its distinct optical and electronic characteristics. However, the low optical absorption and the short carrier lifetime of graphene can limit its use in many applications. Nanocomposites in accordance with various embodiments of the invention integrates metallic nanostructures, such as (but not limited to) plasmonic nanoantennas and metallic nanoparticles, with a graphene-based material to form metallo-graphene nanostructures that can offer high responsivity, ultrafast temporal responses, and broadband operation in a variety of optoelectronic applications.

A system and method for blocking heat from reaching an image sensor in a three dimensional stack with a semiconductor device. In an embodiment a heat sink is formed in a back end of line process either on the semiconductor device or else on the image sensor itself when the image sensor is in a backside illuminated configuration. The heat sink may be a grid in either a single layer or in two layers, a zig-zag pattern, or in an interleaved fingers configuration.

Embodiments of the present application provide an array substrate, a fabrication method for an array substrate, and a display panel. The array substrate includes a substrate, a gate, a gate insulating layer, a seed layer, and a semiconductor layer that are sequentially stacked. A surface of the semiconductor layer away from the seed layer has a concave-convex structure formed by growth of nanocrystalline grains, which enhances light absorption of the semiconductor layer and solves the problems of poor light sensitivity and slow response speed of semiconductor devices.

There is provided a semiconductor device including a memory region and a logic region. The memory region includes a transistor (memory transistor) that stores information by accumulating charge in a sidewall insulating film. The width of the sidewall insulating film of the memory transistor included in the memory region is made larger than the width of a sidewall insulating film of a transistor (logic transistor) included in the logic region.

The present disclosure provides a photoelectric sensor and driving method thereof, as well as an array substrate and a display device. The photoelectric sensor comprises a photoelectric element having an output terminal and a reference level input terminal, an amplifying transistor, a readout transistor, a reset transistor, a capacitor and a plurality of control input terminals. The output terminal of the photoelectric element, the gate of the amplifying transistor and the source of the reset transistor are connected to a first terminal of the capacitor. The reference level input terminal, the sources of the readout transistor and amplifying transistor are connected to a first reference voltage input terminal. The drains of the reset transistor and amplifying transistor are connected to a second reference voltage input terminal. The gates of the read-out transistor and reset transistor are respectively connected to a control input terminal.

The present disclosure relates to a method the present disclosure relates to an integrated chip having an active pixel sensor with a gate dielectric protection layer that reduces damage to an underlying gate dielectric layer during fabrication, and an associated method of formation. In some embodiments, the integrated chip has a photodetector disposed within a substrate, and a gate structure located over the substrate. A gate dielectric protection layer is disposed over the substrate and extends from along a sidewall of the gate structure to a location overlying the photodetector. The gate dielectric protection layer has an upper surface that is vertically below an upper surface of the gate structure.

An integrated circuit is formed by removing a sacrificial gate dielectric layer and a sacrificial gate to form a gate cavity. A conformal dielectric first liner is formed in the gate cavity and a conformal second liner is formed on the first liner. A first etch removes the second liner from the bottom of the gate cavity, leaving material of the second liner on sidewalls of the gate cavity. A second etch removes the first liner from the bottom of the gate cavity exposed by the second liner, leaving material of the first liner on the bottom of the gate cavity under the second liner on the sidewalls of the gate cavity. A third etch removes the second liner from the gate cavity, leaving an L-shaped spacers of the first liner in the gate cavity. A permanent gate dielectric layer and replacement gate are formed in the gate cavity.

An apparatus comprising: a channel (4) configured to conduct charge carriers; and a charge carrier generator (22) configured to generate charge carriers for populating the channel, wherein the charge carrier generator is configured for resonance energy transfer (FRET). The charge carrier generator may be a nanoparticle or quantum dot (22), functionalised with at least one moiety (28A, 28B) to enable detection of an analyte. The charge carrier generator may also be a nanoparticle or quantum dot (22) configured to photo-generate charge carriers. The channel (4) may be made of a material having a very high carrier mobility like graphene or carbon nanotubes.

The present disclosure relates to semiconductor structures and, more particularly, to a self-aligned deep contact for a vertical field effect transistor (VFET) and methods of manufacture. The structure includes a plurality of fin structures, a first contact landing on a substrate material between a first set of fin structures of the plurality of fin structures, sidewalls of the first contact being in direct contact with an insulator material of the first set of the fin structures, and a second contact landing on a work function material between a second set of fin structures of the plurality of fin structures, sidewalls of the second contact being in direct contact with the insulator material of the second set of the fin structures.