A manufacturing method of an array substrate, an array substrate and a display apparatus are provided. The manufacturing method includes: providing a base substrate; sequentially forming an active layer and a first insulating layer that covers the active layer on the base substrate; performing one patterning process on the first insulating layer, so as to form a first through hole and a second through hole that expose the active layer in the first insulating layer, and form a first recess at a surface of the first insulating layer; forming a conductive layer on the patterned first insulating layer, with the conductive layer being filled in the first through hole, the second through hole and the first recess; conducting a grinding process to form a source electrode, a drain electrode and a pixel electrode are formed respectively.

Techniques that can assist with fabricating a package layer that includes a plurality of dual-damascene zero-misalignment-vias (dual-damascene ZMVs) and a trace between the dual-damascene ZMVs are described. The disclosed techniques allow for the dual-damascene ZMVs and their corresponding trace to be plated simultaneously in a single step or operation. As such, there is little or no misalignment between the dual-damascene ZMVs, the trace, and the metal pads connected to the ZMVs. In this way, one or more of the embodiments described herein can assist with reducing manufacturing costs, reducing development time of fabricating a package layer, and with increasing the I/O density in a semiconductor package.

Techniques that can assist with fabricating a package layer that includes a plurality of dual-damascene zero-misalignment-vias (dual-damascene ZMVs) and a trace between the dual-damascene ZMVs are described. The disclosed techniques allow for the dual-damascene ZMVs and their corresponding trace to be plated simultaneously in a single step or operation. As such, there is little or no misalignment between the dual-damascene ZMVs, the trace, and the metal pads connected to the ZMVs. In this way, one or more of the embodiments described herein can assist with reducing manufacturing costs, reducing development time of fabricating a package layer, and with increasing the I/O density in a semiconductor package.

Techniques that can assist with fabricating a package layer that includes a plurality of dual-damascene zero-misalignment-vias (dual-damascene ZMVs) and a trace between the dual-damascene ZMVs are described. The disclosed techniques allow for the dual-damascene ZMVs and their corresponding trace to be plated simultaneously in a single step or operation. As such, there is little or no misalignment between the dual-damascene ZMVs, the trace, and the metal pads connected to the ZMVs. In this way, one or more of the embodiments described herein can assist with reducing manufacturing costs, reducing development time of fabricating a package layer, and with increasing the I/O density in a semiconductor package.

A semiconductor device includes a first insulating interlayer on a substrate, metal lines in the first insulating interlayer, a first air gap between the metal lines in a first region of the substrate and a second air gap between the first insulating interlayer and at least one of the metal lines in a second region of the substrate, a liner layer covering top surfaces and side walls of the metal lines and a top surface and a side wall of the first insulating interlayer, adjacent to the first and second air gaps, and a second insulating interlayer on the liner layer and contacting the liner layer.

A method of forming a semiconductor structure is disclosed. A multi-layer structure is formed over a substrate. A photoresist stack with a stepped sidewall is formed on the multi-layer structure. A pattern of the photoresist stack is transferred to the multi-layer structure.

A method of forming a semiconductor device having a vertical metal line interconnect (via) fully aligned to a first direction of a first interconnect layer and a second direction of a second interconnect layer in a selective recess region by forming a plurality of metal lines in a first dielectric layer; and recessing in a recess region first portions of the plurality of metal lines such that top surfaces of the first portions of the plurality of metal lines are below a top surface of the first dielectric layer; wherein a non-recess region includes second portions of the plurality of metal lines that are outside the recess region.

A manufacturing method of an array substrate, an array substrate and a display apparatus are provided. The manufacturing method includes: providing a base substrate; sequentially forming an active layer and a first insulating layer that covers the active layer on the base substrate; performing one patterning process on the first insulating layer, so as to form a first through hole and a second through hole that expose the active layer in the first insulating layer, and form a first recess at a surface of the first insulating layer; forming a conductive layer on the patterned first insulating layer, with the conductive layer being filled in the first through hole, the second through hole and the first recess; conducting a grinding process to form a source electrode, a drain electrode and a pixel electrode are formed respectively.

A semiconductor device includes a first insulating interlayer on a substrate, metal lines in the first insulating interlayer, a first air gap between the metal lines in a first region of the substrate and a second air gap between the first insulating interlayer and at least one of the metal lines in a second region of the substrate, a liner layer covering top surfaces and side walls of the metal lines and a top surface and a side wall of the first insulating interlayer, adjacent to the first and second air gaps, and a second insulating interlayer on the liner layer and contacting the liner layer.

A method of forming a semiconductor device having a vertical metal line interconnect (via) fully aligned to a first direction of a first interconnect layer and a second direction of a second interconnect layer in a selective recess region by forming a plurality of metal lines in a first dielectric layer; and recessing in a recess region first portions of the plurality of metal lines such that top surfaces of the first portions of the plurality of metal lines are below a top surface of the first dielectric layer; wherein a non-recess region includes second portions of the plurality of metal lines that are outside the recess region.