The present application discloses a semiconductor device with a composite barrier structure and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a first dielectric layer having a feature opening on a substrate; a composite barrier structure in the feature opening, wherein the composite barrier structure includes a barrier layer in the feature opening and an assisting blocking layer on the barrier layer; and a conductive feature on the assisting blocking layer; wherein the barrier layer includes tantalum, and the assisting blocking layer includes copper manganese alloy.

The present application discloses a method for fabricating a semiconductor device including: providing a photomask including an opaque layer on a mask substrate and surrounding a translucent layer on the mask substrate; forming a pre-process mask layer on a device stack; patterning the pre-process mask layer using the photomask to form a patterned mask layer including a mask region corresponding to the opaque layer, a trench region corresponding to the translucent layer, and a via hole corresponding to the mask opening of via feature; performing a damascene etching process to form a via opening and a trench opening in the device stack; and forming a via in the via opening and a trench in the trench opening. The translucent layer includes a mask opening of via feature which exposes a portion of the mask substrate. A thickness of the trench region is less than a thickness of the mask region.

The present disclosure provides a method for fabricating a semiconductor device including providing a photomask including an opaque layer on a mask substrate and surrounding a translucent layer on the mask substrate, wherein the translucent layer includes a mask opening of contact portion which exposes a portion of the mask substrate; providing a stack structure including an etch stop layer on a bottom conductive layer and a first inter-dielectric layer on the etch stop layer, and forming a pre-process mask layer on the stack structure; patterning the pre-process mask layer using the photomask to form a patterned mask layer including a mask region corresponding to the opaque layer, a region of body portion corresponding to the translucent layer, and a hole of contact portion corresponding to the mask opening of contact portion.

A method of forming a semiconductor device having a vertical metal line interconnect (via) fully aligned to a first direction of a first interconnect layer and a second direction of a second interconnect layer in a selective recess region by forming a plurality of metal lines in a first dielectric layer; and recessing in a recess region first portions of the plurality of metal lines such that top surfaces of the first portions of the plurality of metal lines are below a top surface of the first dielectric layer; wherein a non-recess region includes second portions of the plurality of metal lines that are outside the recess region.

A semiconductor device has a semiconductor die. A first dielectric layer is formed over the semiconductor die. A second dielectric layer is formed over the first dielectric layer. A trench is formed in the second dielectric layer. A via opening is formed to expose a contact pad of the semiconductor die within the trench. A seed layer is formed over the second dielectric layer. The seed layer extends into the trench and via opening. A conductive material is deposited into the via opening and trench. The conductive material is overburdened from the trench. The seed layer around the conductive material is etched in a first etching step. The conductive material is etched in a second etching step.

A semiconductor device has a semiconductor die. A first dielectric layer is formed over the semiconductor die. A second dielectric layer is formed over the first dielectric layer. A trench is formed in the second dielectric layer. A via opening is formed to expose a contact pad of the semiconductor die within the trench. A seed layer is formed over the second dielectric layer. The seed layer extends into the trench and via opening. A conductive material is deposited into the via opening and trench. The conductive material is overburdened from the trench. The seed layer around the conductive material is etched in a first etching step. The conductive material is etched in a second etching step.

The present application discloses a semiconductor device with a contact structure. The semiconductor device includes a bottom dielectric layer positioned on a substrate; a bottom conductive layer positioned in the bottom dielectric layer; an etch stop layer positioned on the bottom conductive layer; a first inter-dielectric layer positioned on the etch stop layer; and a contact structure including a body portion positioned along the first inter-dielectric layer and extending to the etch stop layer, and a contact portion positioned in the etch stop layer and contacting the body portion and the bottom conductive layer. A width of the body portion is greater than a width of the contact portion.